參數(shù)資料
型號(hào): XC5204-6TQ144C
廠商: Xilinx Inc
文件頁(yè)數(shù): 39/73頁(yè)
文件大?。?/td> 0K
描述: IC FPGA 120 CLB'S 144-TQFP
產(chǎn)品變化通告: XC1700 PROMs,XC5200,HQ,SCD Parts Discontinuation 19/Jul/2010
標(biāo)準(zhǔn)包裝: 60
系列: XC5200
LAB/CLB數(shù): 120
邏輯元件/單元數(shù): 480
輸入/輸出數(shù): 117
門(mén)數(shù): 6000
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-TQFP(20x20)
其它名稱: 122-1136
R
XC5200 Series Field Programmable Gate Arrays
7-126
November 5, 1998 (Version 5.2)
XC5200 Program Readback Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements.
The following guidelines reflect worst-case values over the recommended operating conditions.
Note 1: Timing parameters apply to all speed grades.
Note 2: rdbk.TRIG is High prior to Finished, Finished will trigger the first Readback
Description
Symbol
Min
Max
Units
rdbk.TRIG
rdbk.TRIG setup to initiate and abort Readback
rdbk.TRIG hold to initiate and abort Readback
1
2
TRTRC
TRCRT
200
50
-
ns
rdclk.1
rdbk.DATA delay
rdbk.RIP delay
High time
Low time
7
6
5
4
TRCRD
TRCRR
TRCH
TRCL
-
250
500
ns
RTRC
T
RCRT
T
2
RCL
T
4
RCRR
T
6
RCH
T
5
RCRD
T
7
DUMMY
rdbk.DATA
rdbk.RIP
rdclk.I
rdbk.TRIG
Finished
Internal Net
VALID
RTL
T
3
X1790
VALID
1
Product Obsolete or Under Obsolescence
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