參數(shù)資料
| 型號： | XC5210-5PC84C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 41/73頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA 324 CLB'S 84-PLCC |
| 產品變化通告： | XC1700 PROMs,XC5200,HQ,SCD Parts Discontinuation 19/Jul/2010 |
| 標準包裝： | 15 |
| 系列： | XC5200 |
| LAB/CLB數(shù)： | 324 |
| 邏輯元件/單元數(shù)： | 1296 |
| 輸入/輸出數(shù)： | 65 |
| 門數(shù)： | 16000 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 84-LCC（J 形引線） |
| 供應商設備封裝： | 84-PLCC |
| 其它名稱： | 122-1144 |
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R
XC5200 Series Field Programmable Gate Arrays
7-128
November 5, 1998 (Version 5.2)
XC5200 Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
XC5200 Longline Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Speed Grade
-6-5-4-3
Description
Symbol
Device
Max
(ns)
Max
(ns)
Max
(ns)
Max
(ns)
Global Signal Distribution
From pad through global buffer, to any clock (CK)
T
BUFG
XC5202
9.1
8.5
8.0
6.9
XC5204
9.3
8.7
8.2
7.6
XC5206
9.4
8.8
8.3
7.7
XC5210
9.4
8.8
8.5
7.7
XC5215
10.5
9.9
9.8
9.6
Speed Grade
-6
-5
-4
-3
Description
Symbol
Device
Max
(ns)
Max
(ns)
Max
(ns)
Max
(ns)
TBUF driving a Longline
I to Longline, while TS is Low; i.e., buffer is constantly ac-
tive
T
IO
XC5202
6.0
3.8
3.0
2.0
XC5204
6.4
4.1
3.2
2.3
XC5206
6.6
4.2
3.3
2.7
XC5210
6.6
4.2
3.3
2.9
XC5215
7.3
4.6
3.8
3.2
TS going Low to Longline going from floating High or Low
to active Low or High
T
ON
XC5202
7.8
5.6
4.7
4.0
XC5204
8.3
5.9
4.9
4.3
XC5206
8.4
6.0
5.0
4.4
XC5210
8.4
6.0
5.0
4.4
XC5215
8.9
6.3
5.3
4.5
TS going High to TBUF going inactive, not driving
Longline
T
OFF
XC52xx
3.0
2.8
2.6
2.4
Note: 1. Die-size-dependent parameters are based upon XC5215 characterization. Production specifications will vary with array
size.
TS
IO
TBUF
Product Obsolete or Under Obsolescence
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XC5210-5PC84I | 制造商:Xilinx 功能描述: |
| XC5210-5PG156C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays |
| XC5210-5PG191C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays |
| XC5210-5PG223C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays |
| XC5210-5PG223I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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