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參數(shù)資料
| 型號： | XC5210-5PC84C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 42/73頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 324 CLB'S 84-PLCC |
| 產(chǎn)品變化通告： | XC1700 PROMs,XC5200,HQ,SCD Parts Discontinuation 19/Jul/2010 |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 系列： | XC5200 |
| LAB/CLB數(shù)： | 324 |
| 邏輯元件/單元數(shù)： | 1296 |
| 輸入/輸出數(shù)： | 65 |
| 門數(shù)： | 16000 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 84-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 84-PLCC |
| 其它名稱： | 122-1144 |
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R
November 5, 1998 (Version 5.2)
7-129
XC5200 Series Field Programmable Gate Arrays
7
XC5200 CLB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Speed Grade
-6
-5
-4
-3
Description
Symbol
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Combinatorial Delays
F inputs to X output
T
ILO
5.6
4.6
3.8
3.0
F inputs via transparent latch to Q
T
ITO
8.0
6.6
5.4
4.3
DI inputs to DO output (Logic-Cell
Feedthrough)
T
IDO
4.3
3.5
2.8
2.4
F inputs via F5_MUX to DO output
T
IMO
7.2
5.8
5.0
4.3
Carry Delays
Incremental delay per bit
T
CY
0.7
0.6
0.5
Carry-in overhead from DI
T
CYDI
1.8
1.6
1.5
1.4
Carry-in overhead from F
T
CYL
3.7
3.2
2.9
2.4
Carry-out overhead to DO
T
CYO
4.0
3.2
2.5
2.1
Sequential Delays
Clock (CK) to out (Q) (Flip-Flop)
T
CKO
5.8
4.9
4.0
Gate (Latch enable) going active to out (Q)
T
GO
9.2
7.4
5.9
5.5
Set-up Time Before Clock (CK)
F inputs
T
ICK
2.3
1.8
1.4
1.3
F inputs via F5_MUX
T
MICK
3.8
3.0
2.5
2.4
DI input
T
DICK
0.8
0.5
0.4
CE input
T
EICK
1.6
1.2
0.9
Hold Times After Clock (CK)
F inputs
T
CKI
00
0
F inputs via F5_MUX
T
CKMI
00
0
DI input
T
CKDI
00
0
CE input
T
CKEI
00
0
Clock Widths
Clock High Time
T
CH
6.0
Clock Low Time
T
CL
6.0
Toggle Frequency (MHz) (Note 3)
FTOG
83
Reset Delays
Width (High)
T
CLRW
6.0
Delay from CLR to Q (Flip-Flop)
T
CLR
7.7
6.3
5.1
4.0
Delay from CLR to Q (Latch)
T
CLRL
6.5
5.2
4.2
3.0
Global Reset Delays
Width (High)
T
GCLRW
6.0
Delay from internal GR to Q
T
GCLR
14.7
12.1
9.1
8.0
Note: 1. The CLB K to Q output delay (TCKO) of any CLB, plus the shortest possible interconnect delay, is always longer than the
Data In hold-time requirement (TCKDI) of any CLB on the same die.
2. Timing is based upon the XC5215 device. For other devices, see Timing Calculator.
3. Maximum flip-flop toggle rate for export control purposes.
Product Obsolete or Under Obsolescence
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