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參數資料
| 型號： | XC5210-5PG223I |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | 現場可編程門陣列（FPGA） |
| 文件頁數： | 48/73頁 |
| 文件大?。?/td> | 598K |
| 代理商： | XC5210-5PG223I |
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R
XC5200 Series Field Programmable Gate Arrays
7-130
November 5, 1998 (Version 5.2)
XC5200 Guaranteed Input and Output Parameters (Pin-to-Pin)
All values listed below are tested directly, and guaranteed over the operating conditions. The same parameters can also be
derived indirectly from the Global Buffer specifications. The delay calculator uses this indirect method, and may
overestimate because of worst-case assumptions. When there is a discrepancy between these two methods, the values
listed below should be used, and the derived values should be considered conservative overestimates.
Speed Grade
-6
-5
-4
-3
Description
Symbol
Device
Max
(ns)
16.9
17.1
17.2
17.2
19.0
21.4
21.6
21.7
21.7
24.3
2.5
2.3
2.2
2.2
2.0
3.8
3.9
4.4
5.1
5.8
7.3
7.3
7.2
7.2
6.8
8.8
8.6
8.5
8.5
8.5
0
Max
(ns)
15.1
15.3
15.4
15.4
17.0
18.7
18.9
19.0
19.0
21.2
2.0
1.9
1.9
1.9
1.8
3.8
3.9
4.4
5.1
5.8
6.6
6.6
6.5
6.5
5.7
7.7
7.5
7.4
7.4
7.4
0
Max
(ns)
10.9
11.3
11.9
12.8
12.8
12.6
13.3
13.6
15.0
15.0
1.9
1.9
1.9
1.9
1.7
3.5
3.8
4.4
4.9
5.7
6.6
6.6
6.4
6.0
5.7
7.5
7.5
7.4
7.4
7.4
0
Max
(ns)
9.8
9.9
10.8
11.2
11.7
11.5
11.9
12.5
12.9
13.1
1.9
1.9
1.9
1.8
1.7
3.5
3.6
4.3
4.8
5.6
6.6
6.6
6.3
6.0
5.7
7.5
7.5
7.4
7.3
7.2
0
Global Clock to Output Pad (fast)
T
ICKOF
(Max)
XC5202
XC5204
XC5206
XC5210
XC5215
XC5202
XC5204
XC5206
XC5210
XC5215
XC5202
XC5204
XC5206
XC5210
XC5215
XC5202
XC5204
XC5206
XC5210
XC5215
XC5202
XC5204
XC5206
XC5210
XC5215
XC5202
XC5204
XC5206
XC5210
XC5215
XC52xx
Global Clock to Output Pad (slew-limited)
T
ICKO
(Max)
Input Set-up Time (no delay) to CLB Flip-Flop
IOB
(NODELAY)Connect
T
PSUF
(Min)
Input Hold Time (no delay) to CLB Flip-Flop
IOB
(NODELAY)
T
PHF
(Min)
Input Set-up Time (with delay) to CLB Flip-Flop DI Input
IOB
T
PSU
Input Set-up Time (with delay) to CLB Flip-Flop F Input
IOB
Direct
T
PSU
L
(Min)
Input Hold Time (with delay) to CLB Flip-Flop
IOB
T
PH
(Min)
Note:
1. These measurements assume that the CLB flip-flop uses a direct interconnect to or from the IOB. The INREG/ OUTREG
properties, or XACT-Performance, can be used to assure that direct connects are used. t
applies only to the CLB input
DI that bypasses the look-up table, which only offers direct connects to IOBs on the left and right edges of the die. t
applies to the CLB inputs F that feed the look-up table, which offers direct connect to IOBs on all four edges, as do the CLB
Q outputs.
2. When testing outputs (fast or slew-limited), half of the outputs on one side of the device are switching.
Global Clock-to-Output Delay
Q
.
Direct
IOB
CLB
FAST
BUFG
Global Clock-to-Output Delay
Q
.
Direct
IOB
CLB
BUFG
Time
F,DI
CLB
BUFG
Time
Direct
CLB
F,DI
BUFG
Time
Direct
Connect
CLB
DI
BUFG
Time
CLB
F
BUFG
Time
Direct
CLB
BUFG
F,DI
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