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參數(shù)資料
| 型號(hào)： | XC5210-5PQ240C |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 13/73頁(yè) |
| 文件大小： | 0K |
| 描述： | IC FPGA 324 CLB'S 240-PQFP |
| 產(chǎn)品變化通告： | XC1700 PROMs,XC5200,HQ,SCD Parts Discontinuation 19/Jul/2010 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | XC5200 |
| LAB/CLB數(shù)： | 324 |
| 邏輯元件/單元數(shù)： | 1296 |
| 輸入/輸出數(shù)： | 196 |
| 門數(shù)： | 16000 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 240-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 240-PQFP（32x32） |
| 其它名稱： | 122-1150 |
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R
XC5200 Series Field Programmable Gate Arrays
7-102
November 5, 1998 (Version 5.2)
tions During Configuration” on page 124, in the “Configura-
tion Timing” section.
Table 9: Pin Descriptions
Pin Name
I/O
During
Config.
I/O
After
Config.
Pin Description
Permanently Dedicated Pins
VCC
I
Five or more (depending on package) connections to the nominal +5 V supply voltage.
All must be connected, and each must be decoupled with a 0.01 - 0.1
F capacitor to
Ground.
GND
I
Four or more (depending on package type) connections to Ground. All must be con-
nected.
CCLK
I or O
I
During configuration, Configuration Clock (CCLK) is an output in Master modes or Asyn-
chronous Peripheral mode, but is an input in Slave mode, Synchronous Peripheral
mode, and Express mode. After configuration, CCLK has a weak pull-up resistor and
can be selected as the Readback Clock. There is no CCLK High time restriction on
XC5200-Series devices, except during Readback. See “Violating the Maximum High
and Low Time Specification for the Readback Clock” on page 113 for an explanation of
this exception.
DONE
I/O
O
DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, it
indicates the completion of the configuration process. As an input, a Low level on
DONE can be configured to delay the global logic initialization and the enabling of out-
puts.
The exact timing, the clock source for the Low-to-High transition, and the optional
pull-up resistor are selected as options in the program that creates the configuration bit-
stream. The resistor is included by default.
PROGRAM
II
PROGRAM is an active Low input that forces the FPGA to clear its configuration mem-
ory. It is used to initiate a configuration cycle. When PROGRAM goes High, the FPGA
executes a complete clear cycle, before it goes into a WAIT state and releases INIT.
The PROGRAM pin has an optional weak pull-up after configuration.
User I/O Pins That Can Have Special Functions
RDY/BUSY
OI/O
During Peripheral mode configuration, this pin indicates when it is appropriate to write
another byte of data into the FPGA. The same status is also available on D7 in Asyn-
chronous Peripheral mode, if a read operation is performed when the device is selected.
After configuration, RDY/BUSY is a user-programmable I/O pin.
RDY/BUSY is pulled High with a high-impedance pull-up prior to INIT going High.
RCLK
OI/O
During Master Parallel configuration, each change on the A0-A17 outputs is preceded
by a rising edge on RCLK, a redundant output signal. RCLK is useful for clocked
PROMs. It is rarely used during configuration. After configuration, RCLK is a user-pro-
grammable I/O pin.
M0, M1, M2
I
I/O
As Mode inputs, these pins are sampled before the start of configuration to determine
the configuration mode to be used. After configuration, M0, M1, and M2 become us-
er-programmable I/O.
During configuration, these pins have weak pull-up resistors. For the most popular con-
figuration mode, Slave Serial, the mode pins can thus be left unconnected. A pull-down
resistor value of 3.3 k
is recommended for other modes.
TDO
O
If boundary scan is used, this pin is the Test Data Output. If boundary scan is not used,
this pin is a 3-state output, after configuration is completed.
This pin can be user output only when called out by special schematic definitions. To
use this pin, place the library component TDO instead of the usual pad symbol. An out-
put buffer must still be used.
Product Obsolete or Under Obsolescence
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