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參數(shù)資料
| 型號： | XC5210-6PQ208C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 1/73頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 324 CLB'S 208-PQFP |
| 產(chǎn)品變化通告： | XC1700 PROMs,XC5200,HQ,SCD Parts Discontinuation 19/Jul/2010 |
| 標準包裝： | 24 |
| 系列： | XC5200 |
| LAB/CLB數(shù)： | 324 |
| 邏輯元件/單元數(shù)： | 1296 |
| 輸入/輸出數(shù)： | 164 |
| 門數(shù)： | 16000 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 208-BFQFP |
| 供應商設備封裝： | 208-PQFP（28x28） |
| 其它名稱： | 122-1149 |
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November 5, 1998 (Version 5.2)
7-83
7
Features
Low-cost, register/latch rich, SRAM based
reprogrammable architecture
-0.5
m three-layer metal CMOS process technology
-
256 to 1936 logic cells (3,000 to 23,000 “gates”)
-
Price competitive with Gate Arrays
System Level Features
-
System performance beyond 50 MHz
-
6 levels of interconnect hierarchy
-
VersaRing I/O Interface for pin-locking
-
Dedicated carry logic for high-speed arithmetic
functions
-
Cascade chain for wide input functions
-
Built-in IEEE 1149.1 JTAG boundary scan test
circuitry on all I/O pins
-
Internal 3-state bussing capability
-
Four dedicated low-skew clock or signal distribution
nets
Versatile I/O and Packaging
-
Innovative VersaRing I/O interface provides a high
logic cell to I/O ratio, with up to 244 I/O signals
-
Programmable output slew-rate control maximizes
performance and reduces noise
-
Zero Flip-Flop hold time for input registers simplifies
system timing
-
Independent Output Enables for external bussing
-
Footprint compatibility in common packages within
the XC5200 Series and with the XC4000 Series
-
Over 150 device/package combinations, including
advanced BGA, TQ, and VQ packaging available
Fully Supported by Xilinx Development System
-
Automatic place and route software
-
Wide selection of PC and Workstation platforms
-
Over 100 3rd-party Alliance interfaces
-
Supported by shrink-wrap Foundation software
Description
The XC5200 Field-Programmable Gate Array Family is
engineered to deliver low cost. Building on experiences
gained with three previous successful SRAM FPGA fami-
lies, the XC5200 family brings a robust feature set to pro-
grammable logic design. The VersaBlock logic module,
the VersaRing I/O interface, and a rich hierarchy of inter-
connect resources combine to enhance design flexibility
and reduce time-to-market. Complete support for the
XC5200 family is delivered through the familiar Xilinx soft-
ware environment. The XC5200 family is fully supported on
popular workstation and PC platforms. Popular design
entry methods are fully supported, including ABEL, sche-
matic capture, VHDL, and Verilog HDL synthesis. Design-
ers utilizing logic synthesis can use their existing tools to
design with the XC5200 devices.
.
0
XC5200 Series
Field Programmable Gate Arrays
November 5, 1998 (Version 5.2)
07*
Product Specification
R
Table 1: XC5200 Field-Programmable Gate Array Family Members
Device
XC5202
XC5204
XC5206
XC5210
XC5215
Logic Cells
256
480
784
1,296
1,936
Max Logic Gates
3,000
6,000
10,000
16,000
23,000
Typical Gate Range
2,000 - 3,000
4,000 - 6,000
6,000 - 10,000
10,000 - 16,000 15,000 - 23,000
VersaBlock Array
8 x 8
10 x 12
14 x 14
18 x 18
22 x 22
CLBs
64
120
196
324
484
Flip-Flops
256
480
784
1,296
1,936
I/Os
84
124
148
196
244
TBUFs per Longline
1014162024
Product Obsolete or Under Obsolescence
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XC5210-6PQ208C0167 | 制造商:Xilinx 功能描述: |
| XC5210-6PQ208I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| XC5210-6PQ240C | 功能描述:IC FPGA 324 CLB'S 240-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC5200 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應商設備封裝:120-CPGA（34.55x34.55） |
| XC5210-6PQ240I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| XC5210-6PQG208C | 制造商:Xilinx 功能描述: |
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