參數(shù)資料
型號(hào)： XC5215-5PG299I
英文描述： Field Programmable Gate Array (FPGA)
中文描述： 現(xiàn)場(chǎng)可編程門(mén)陣列（FPGA）
文件頁(yè)數(shù)： 37/73頁(yè)
文件大小： 598K
代理商： XC5215-5PG299I
R
November 5, 1998 (Version 5.2)
7-119
XC5200 Series Field Programmable Gate Arrays
7
Notes:
1. Peripheral Synchronous mode can be considered Slave Parallel mode. An external CCLK provides timing, clocking in the
first
data byte on the
second
rising edge of CCLK after INIT goes high. Subsequent data bytes are clocked in on every
eighth consecutive rising edge of CCLK.
2. The RDY/BUSY line goes High for one CCLK period after data has been clocked in, although synchronous operation does
not require such a response.
3. The pin name RDY/BUSY is a misnomer. In synchronous peripheral mode this is really an ACKNOWLEDGE signal.
4.Note that data starts to shift out serially on the DOUT pin 0.5 CCLK periods after it was loaded in parallel. Therefore,
additional CCLK pulses are clearly required after the last byte has been loaded.
Figure 34: Synchronous Peripheral Mode Programming Switching Characteristics
0
DOUT
CCLK
1
2
3
4
5
6
7
BYTE
0
BYTE
1
BYTE 0 OUT
BYTE 1 OUT
RDY/BUSY
INIT
1
0
X6096
T
CCL
D0 - D7
T
IC
T
CD
T
DC
1
2
3
Description
Symbol
Min
5
60
0
50
60
Max
Units
μ
s
ns
ns
ns
ns
MHz
CCLK
INIT (High) setup time
D0 - D7 setup time
D0 - D7 hold time
CCLK High time
CCLK Low time
CCLK Frequency
1
2
3
T
IC
T
DC
T
CD
T
CCH
T
CCL
F
CC
8
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