參數(shù)資料
型號(hào)： XC5215
廠商： Xilinx, Inc.
英文描述： Field Programmable Gate Arrays(現(xiàn)場(chǎng)可編程門(mén)陣列)
中文描述： 現(xiàn)場(chǎng)可編程門(mén)陣列（現(xiàn)場(chǎng)可編程門(mén)陣列）
文件頁(yè)數(shù)： 14/73頁(yè)
文件大?。?/td> 598K
代理商： XC5215
R
XC5200 Series Field Programmable Gate Arrays
7-96
November 5, 1998 (Version 5.2)
segments span the width and height of the chip,
respectively.
Two low-skew horizontal and vertical unidirectional glo-
bal-line segments span each row and column of the chip,
respectively.
Single- and Double-Length Lines
The single- and double-length bidirectional line segments
make up the bulk of the routing channels. The dou-
ble-length lines hop across every other CLB to reduce the
propagation delays in speed-critical nets. Regenerating the
signal strength is recommended after traversing three or
four such segments. Xilinx place-and-route software auto-
matically connects buffers in the path of the signal as nec-
essary. Single- and double-length lines cannot drive onto
Longlines and global lines; Longlines and global lines can,
however, drive onto single- and double-length lines. As a
general rule, Longline and global-line connections to the
general routing matrix are unidirectional, with the signal
direction from these lines toward the routing matrix.
Longlines
Longlines are used for high-fan-out signals, 3-state busses,
low-skew nets, and faraway destinations. Row and column
splitter PIPs in the middle of the array effectively double the
total number of Longlines by electrically dividing them into
two separated half-lines. Longlines are driven by the
3-state buffers in each CLB, and are driven by similar buff-
ers at the periphery of the array from the VersaRing I/O
Interface.
Bus-oriented designs are easily implemented by using Lon-
glines in conjunction with the 3-state buffers in the CLB and
in the VersaRing. Additionally, weak keeper cells at the
periphery retain the last valid logic level on the Longlines
when all buffers are in 3-state mode.
Longlines connect to the single-length or double-length
lines, or to the logic inside the CLB, through the General
Routing Matrix. The only manner in which a Longline can
be driven is through the four 3-state buffers; therefore, a
Longline-to-Longline or single-line-to-Longline connection
through PIPs in the General Routing Matrix is not possible.
Again, as a general rule, long- and global-line connections
to the General Routing Matrix are unidirectional, with the
signal direction from these lines toward the routing matrix.
The XC5200 family has no pull-ups on the ends of the Lon-
glines sourced by TBUFs, unlike the XC4000 Series. Con-
sequently, wired functions (i.e., WAND and WORAND) and
wide multiplexing functions requiring pull-ups for undefined
states (i.e., bus applications) must be implemented in a dif-
ferent way. In the case of the wired functions, the same
functionality can be achieved by taking advantage of the
carry/cascade logic described above, implementing a wide
logic function in place of the wired function. In the case of
3-state bus applications, the user must insure that all states
of the multiplexing function are defined. This process is as
simple as adding an additional TBUF to drive the bus High
when the previously undefined states are activated.
Global Lines
Global buffers in Xilinx FPGAs are special buffers that drive
a dedicated routing network called Global Lines, as shown
in
Figure 16
. This network is intended for high-fanout
clocks or other control signals, to maximize speed and min-
imize skewing while distributing the signal to many loads.
The XC5200 family has a total of four global buffers (BUFG
symbol in the library), each with its own dedicated routing
channel. Two are distributed vertically and two horizontally
throughout the FPGA.
The global lines provide direct input only to the CLB clock
pins. The global lines also connect to the General Routing
Matrix to provide access from these lines to the function
generators and other control signals.
Four clock input pads at the corners of the chip, as shown
in
Figure 16
, provide a high-speed, low-skew clock network
to each of the four global-line buffers. In addition to the ded-
icated pad, the global lines can be sourced by internal
logic. PIPs from several routing channels within the Ver-
saRing can also be configured to drive the global-line buff-
ers.
Details of all the programmable interconnect for a CLB is
shown in
Figure 17
.
Figure 16: Global Lines
GCK1
GCK4
GCK3
GCK2
X5704
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