鍨嬭櫉锛� | XC5VLX50-3FF1153C |
寤犲晢锛� | Xilinx Inc |
鏂囦欢闋佹暩(sh霉)锛� | 45/91闋� |
鏂囦欢澶�?銆�?/td> | 0K |
鎻忚堪锛� | IC FPGA VIRTEX-5 50K 1153FBGA |
妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
绯诲垪锛� | Virtex®-5 LX |
LAB/CLB鏁�(sh霉)锛� | 3600 |
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� | 46080 |
RAM 浣嶇附瑷�(j矛)锛� | 1769472 |
杓稿叆/杓稿嚭鏁�(sh霉)锛� | 560 |
闆绘簮闆诲锛� | 0.95 V ~ 1.05 V |
瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
宸ヤ綔婧害锛� | 0°C ~ 85°C |
灏佽/澶栨锛� | 1153-BBGA锛孎(xi脿n)CBGA |
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 1153-FCBGA锛�35x35锛� |
閰嶇敤锛� | 568-5088-ND - BOARD DEMO DAC1408D750 HW-V5-ML561-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5 HW-V5-ML550-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5 HW-V5-ML521-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5 HW-AFX-FF1153-500-G-ND - BOARD DEV VIRTEX 5 FF1153 HW-V5GBE-DK-UNI-G-ND - KIT DEV V5 LXT GIGABIT ETHERNET 122-1508-ND - EVALUATION PLATFORM VIRTEX-5 |
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
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XC5VLX50-2FFG1153I | IC FPGA VIRTEX-5 50K 1153FBGA |
XC5VLX50-2FF1153I | IC FPGA VIRTEX-5 50K 1153FBGA |
ACB105DHRD | CONN CARD EXTEND 210POS .050" |
ABB105DHRD | CONN CARD EXTEND 210POS .050" |
ACB100DHLT | CONN EDGECARD 200PS .050 DIP SLD |
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
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XC5VLX50-3FF324C | 鍔熻兘鎻忚堪:IC FPGA VIRTEX-5 50K 324FBGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:Virtex®-5 LX 鐢�(ch菐n)鍝佽畩鍖栭€氬憡:Step Intro and Pkg Change 11/March/2008 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:Virtex®-5 SXT LAB/CLB鏁�(sh霉):4080 閭忚集鍏冧欢/鍠厓鏁�(sh霉):52224 RAM 浣嶇附瑷�(j矛):4866048 杓稿叆/杓稿嚭鏁�(sh霉):480 闁€鏁�(sh霉):- 闆绘簮闆诲:0.95 V ~ 1.05 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 100°C 灏佽/澶栨:1136-BBGA锛孎(xi脿n)CBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:1136-FCBGA 閰嶇敤:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
XC5VLX50-3FF676C | 鍔熻兘鎻忚堪:IC FPGA VIRTEX-5 50K 676FBGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:Virtex®-5 LX 鐢�(ch菐n)鍝佽畩鍖栭€氬憡:Step Intro and Pkg Change 11/March/2008 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:Virtex®-5 SXT LAB/CLB鏁�(sh霉):4080 閭忚集鍏冧欢/鍠厓鏁�(sh霉):52224 RAM 浣嶇附瑷�(j矛):4866048 杓稿叆/杓稿嚭鏁�(sh霉):480 闁€鏁�(sh霉):- 闆绘簮闆诲:0.95 V ~ 1.05 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 100°C 灏佽/澶栨:1136-BBGA锛孎(xi脿n)CBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:1136-FCBGA 閰嶇敤:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
XC5VLX50-3FFG1153C | 鍔熻兘鎻忚堪:IC FPGA VIRTEX-5 50K 1153FBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:Virtex®-5 LX 鐢�(ch菐n)鍝佽畩鍖栭€氬憡:Step Intro and Pkg Change 11/March/2008 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:Virtex®-5 SXT LAB/CLB鏁�(sh霉):4080 閭忚集鍏冧欢/鍠厓鏁�(sh霉):52224 RAM 浣嶇附瑷�(j矛):4866048 杓稿叆/杓稿嚭鏁�(sh霉):480 闁€鏁�(sh霉):- 闆绘簮闆诲:0.95 V ~ 1.05 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 100°C 灏佽/澶栨:1136-BBGA锛孎(xi脿n)CBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:1136-FCBGA 閰嶇敤:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
XC5VLX50-3FFG324C | 鍔熻兘鎻忚堪:IC FPGA VIRTEX-5 50K 324FBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:Virtex®-5 LX 鐢�(ch菐n)鍝佽畩鍖栭€氬憡:Step Intro and Pkg Change 11/March/2008 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:Virtex®-5 SXT LAB/CLB鏁�(sh霉):4080 閭忚集鍏冧欢/鍠厓鏁�(sh霉):52224 RAM 浣嶇附瑷�(j矛):4866048 杓稿叆/杓稿嚭鏁�(sh霉):480 闁€鏁�(sh霉):- 闆绘簮闆诲:0.95 V ~ 1.05 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 100°C 灏佽/澶栨:1136-BBGA锛孎(xi脿n)CBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:1136-FCBGA 閰嶇敤:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
XC5VLX50-3FFG676C | 鍔熻兘鎻忚堪:IC FPGA VIRTEX-5 50K 676-FBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:Virtex®-5 LX 鐢�(ch菐n)鍝佽畩鍖栭€氬憡:Step Intro and Pkg Change 11/March/2008 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:Virtex®-5 SXT LAB/CLB鏁�(sh霉):4080 閭忚集鍏冧欢/鍠厓鏁�(sh霉):52224 RAM 浣嶇附瑷�(j矛):4866048 杓稿叆/杓稿嚭鏁�(sh霉):480 闁€鏁�(sh霉):- 闆绘簮闆诲:0.95 V ~ 1.05 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 100°C 灏佽/澶栨:1136-BBGA锛孎(xi脿n)CBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:1136-FCBGA 閰嶇敤:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |