參數(shù)資料
型號(hào)： XC5VSX50T-1FF665C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 5/91頁(yè)
文件大?。?/td> 0K
描述： IC FPGA VIRTEX-5 50K 665FCBGA
產(chǎn)品變化通告： Step Intro and Pkg Change 11/March/2008
標(biāo)準(zhǔn)包裝： 1
系列： Virtex®-5 SXT
LAB/CLB數(shù)： 4080
邏輯元件/單元數(shù)： 52224
RAM 位總計(jì)： 4866048
輸入/輸出數(shù)： 360
電源電壓： 0.95 V ~ 1.05 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 665-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 665-FCBGA
配用： 568-5088-ND - BOARD DEMO DAC1408D750
122-1796-ND - EVALUATION PLATFORM VIRTEX-5
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
13
GTP_DUAL Tile Specifications
GTP_DUAL Tile DC Characteristics
Table 24: Absolute Maximum Ratings for GTP_DUAL Tiles
Symbol
Description
Units
MGTAVCCPLL
Analog supply voltage for the GTP_DUAL shared PLL relative to GND
–0.5 to 1.32
V
MGTAVTTTX
Analog supply voltage for the GTP_DUAL transmitters relative to GND
–0.5 to 1.32
V
MGTAVTTRX
Analog supply voltage for the GTP_DUAL receivers relative to GND
–0.5 to 1.32
V
MGTAVCC
Analog supply voltage for the GTP_DUAL common circuits relative to GND
–0.5 to 1.1
V
MGTAVTTRXC
Analog supply voltage for the resistor calibration circuit of the GTP_DUAL
column
–0.5 to 1.32
V
Notes:
1.
Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
Table 25: Recommended Operating Conditions for GTP_DUAL Tiles(1)(2)
Symbol
Description
Min
Max
Units
MGTAVCCPLL(1)
Analog supply voltage for the GTP_DUAL shared PLL relative to GND
1.14
1.26
V
MGTAVTTTX(1)
Analog supply voltage for the GTP_DUAL transmitters relative to GND
1.14
1.26
V
MGTAVTTRX(1)
Analog supply voltage for the GTP_DUAL receivers relative to GND
1.14
1.26
V
MGTAVCC(1)
Analog supply voltage for the GTP_DUAL common circuits relative to GND
0.95
1.05
V
MGTAVTTRXC(1) Analog supply voltage for the resistor calibration circuit of the GTP_DUAL
column
1.14
1.26
V
Notes:
1.
Each voltage listed requires the filter circuit described in UG196: Virtex-5 FPGA RocketIO GTP Transceiver User Guide.
2.
Voltages are specified for the temperature range of TJ = –40°C to +100°C.
Table 26: DC Characteristics Over Recommended Operating Conditions for GTP_DUAL Tiles(1)
Symbol
Description
Min
Typ
Max
Units
IMGTAVTTTX
GTP_DUAL tile transmitter termination supply current(2)
71
90
mA
IMGTAVCCPLL
GTP_DUAL tile shared PLL supply current
36
60
mA
IMGTAVTTRXC
GTP_DUAL tile resistor termination calibration supply current
0.1
0.5
mA
IMGTAVTTRX
GTP_DUAL tile receiver termination supply current(3)
0.1
0.5
mA
IMGTAVCC
GTP_DUAL tile internal analog supply current
56
110
mA
MGTRREF
Precision reference resistor for internal calibration termination
49.9 ± 1% tolerance
Ω
Notes:
1.
Typical values are specified at nominal voltage, 25°C, with a 3.2 Gb/s line rate.
2.
ICC numbers are given per GTP_DUAL tile with both GTP transceivers operating with default settings.
3.
AC coupled TX/RX link.
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