參數(shù)資料
型號(hào): XC5VSX50T-1FF665C
廠商: Xilinx Inc
文件頁(yè)數(shù): 7/91頁(yè)
文件大?。?/td> 0K
描述: IC FPGA VIRTEX-5 50K 665FCBGA
產(chǎn)品變化通告: Step Intro and Pkg Change 11/March/2008
標(biāo)準(zhǔn)包裝: 1
系列: Virtex®-5 SXT
LAB/CLB數(shù): 4080
邏輯元件/單元數(shù): 52224
RAM 位總計(jì): 4866048
輸入/輸出數(shù): 360
電源電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 665-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 665-FCBGA
配用: 568-5088-ND - BOARD DEMO DAC1408D750
122-1796-ND - EVALUATION PLATFORM VIRTEX-5
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
15
Table 29 summarizes the DC specifications of the clock input of the GTP_DUAL tile. Figure 3 shows the single-ended input
voltage swing. Figure 4 shows the peak-to-peak differential clock input voltage swing. Consult UG196: Virtex-5 FPGA
RocketIO GTP Transceiver User Guide for further details.
X-Ref Target - Figure 2
Figure 2: Peak-to-Peak Differential Output Voltage
Table 29: GTP_DUAL Tile Clock DC Input Specifications(1)
Symbol
DC Parameter
Conditions
Min
Typ
Max
Units
VIDIFF
Differential peak-to-peak input voltage
200
800
2000
mV
VISE
Single-ended input voltage
100
400
1000
mV
RIN
Differential input resistance
80
105
130
Ω
CEXT
Required external AC coupling capacitor
75
100
200
nF
Notes:
1.
VMIN = 0V and VMAX = 1200mV
X-Ref Target - Figure 3
Figure 3: Single-Ended Clock Input Voltage Swing Peak-to-Peak
X-Ref Target - Figure 4
Figure 4: Differential Clock Input Voltage Swing Peak-to-Peak
0
+V
–V
P–N
DVPPOUT
ds202_02_081809
0
+V
P
N
VISE
ds202_03_052708
0
+V
–V
P – N
VIDIFF
ds202_04_052708
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