參數(shù)資料
型號(hào): XC5VTX150T-2FFG1156I
廠商: Xilinx Inc
文件頁(yè)數(shù): 39/91頁(yè)
文件大?。?/td> 0K
描述: IC FPGA VIRTEX5TXT 150K 1156FBGA
產(chǎn)品培訓(xùn)模塊: PCI Express and Virtex® -5 FPGAs
標(biāo)準(zhǔn)包裝: 1
系列: Virtex®-5 TXT
LAB/CLB數(shù): 11600
邏輯元件/單元數(shù): 148480
RAM 位總計(jì): 8404992
輸入/輸出數(shù): 360
電源電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 1156-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1156-FCBGA(35x35)
配用: 568-5088-ND - BOARD DEMO DAC1408D750
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
44
Input/Output Delay Switching Characteristics
CLB Switching Characteristics
Table 64: Input/Output Delay Switching Characteristics
Symbol
Description
Speed Grade
Units
-3
-2
-1
IDELAYCTRL
TIDELAYCTRLCO_RDY
Reset to Ready for IDELAYCTRL
3.00
s
FIDELAYCTRL_REF
REFCLK frequency
200.00
MHz
IDELAYCTRL_REF_PRECISION
REFCLK precision
±10
MHz
TIDELAYCTRL_RPW
Minimum Reset pulse width
50.00
ns
IODELAY
TIDELAYRESOLUTION
IODELAY Chain Delay Resolution
1/(64 x FREF x1e6)(1)
ps
TIDELAYPAT_JIT
Pattern dependent period jitter in delay chain
for clock pattern
000
Note 2
Pattern dependent period jitter in delay chain
for random data pattern (PRBS 23)
±5
Note 2
TIODELAY_CLK_MAX
Maximum frequency of CLK input to IODELAY
300
250
MHz
TIODCCK_CE / TIODCKC_CE
CE pin Setup/Hold with respect to CK
0.29
–0.06
0.34
–0.06
0.42
–0.06
ns
TIODCK_INC/ TIODCKC_INC
INC pin Setup/Hold with respect to CK
0.18
0.02
0.20
0.04
0.24
0.06
ns
TIODCK_RST/ TIODCKC_RST
RST pin Setup/Hold with respect to CK
0.25
–0.12
0.28
–0.12
0.33
–0.12
ns
TIODDO_T
TSCONTROL delay to MUXE/MUXF switching
and through IODELAY
Note 3
TIODDO_IDATAIN
Propagation delay through IODELAY
Note 3
TIODDO_ODATAIN
Propagation delay through IODELAY
Note 3
Notes:
1.
Average Tap Delay at 200 MHz = 78 ps.
2.
Units in ps, peak-to-peak per tap, in High Performance mode.
3.
Delay depends on IODELAY tap setting. See TRACE report for actual values.
Table 65: CLB Switching Characteristics
Symbol
Description
Speed Grade
Units
-3
-2
-1
Combinatorial Delays
TILO
An – Dn LUT address to A
0.08
0.09
0.10
ns, Max
An – Dn LUT address to AMUX/CMUX
0.20
0.22
0.25
ns, Max
An – Dn LUT address to BMUX_A
0.31
0.35
0.40
ns, Max
TITO
An – Dn inputs to A – D Q outputs
0.67
0.77
0.90
ns, Max
TAXA
AX inputs to AMUX output
0.39
0.44
0.53
ns, Max
TAXB
AX inputs to BMUX output
0.46
0.52
0.61
ns, Max
TAXC
AX inputs to CMUX output
0.31
0.36
0.42
ns, Max
TAXD
AX inputs to DMUX output
0.55
0.62
0.73
ns, Max
TBXB
BX inputs to BMUX output
0.36
0.41
0.48
ns, Max
TBXD
BX inputs to DMUX output
0.45
0.51
0.59
ns, Max
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