參數(shù)資料
型號: XC6SLX100T-N3CSG484I
廠商: Xilinx Inc
文件頁數(shù): 2/11頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN-6 484CSBGA
標準包裝: 84
系列: Spartan® 6 LXT
LAB/CLB數(shù): 7911
邏輯元件/單元數(shù): 101261
RAM 位總計: 4939776
輸入/輸出數(shù): 296
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 484-FBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 484-CSPBGA
Spartan-6 Family Overview
DS160 (v2.0) October 25, 2011
Product Specification
10
Notice of Disclaimer
The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the
maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL
WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
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(whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related
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any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility
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You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to
the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to
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03/03/10
1.4
Updated the slice counts for the LX25 and LX25T in Table 1. Revised the Dynamic Reconfiguration
Port section. Added to the Spread-Spectrum Clocking section. Changed the PLL VCO maximum
frequency to 1080 MHz and the DSP48A1 slice maximum frequency to 320 MHz due to the addition
of the -4 speed specification. Clarified configurations in the Programmable Data Width section.
Updated Low-Power Gigabit Transceiver operating rate.
08/02/10
1.5
Updated data transfer rate per differential I/O from 1,050 Mb/s to 1,080 Mb/s in Summary of Spartan-6
FPGA Features. Added the -3N speed grade to appropriate section throughout the document,
including Figure 1. Updated category in Table 2 from Size to Body Size. Updated the Configuration
section with SPI and BPI interface information. Removed the Dynamic Reconfiguration Port section.
Updated the operating speed of the DSP48A1 slice multiplier and accumulator to 390 MHz in Digital
11/05/10
1.6
transceiver data rate to 3.2 Gb/s. Updated the notes in Figure 1. Added
DS170, XA Spartan-6
Automotive FPGA Family Overview to the Spartan-6 FPGA Documentation.
03/21/11
1.7
Updated from Advance to Preliminary Specification. Removed -4 speed grade from Summary of
10/25/11
2.0
Updated from Preliminary Specification to Production Specification. Updated Configuration, including
the range of configuration bits to 3 Mb and 33 Mb, and Input and Output Delay. Updated Spartan-6
(DS172) to list of documentation.
Date
Version
Description of Revisions
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