Spartan-6 Family Overview
DS160 (v2.0) October 25, 2011
Product Specification
10
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03/03/10
1.4
Updated the slice counts for the LX25 and LX25T in
Table 1. Revised the Dynamic Reconfiguration
frequency to 1080 MHz and the DSP48A1 slice maximum frequency to 320 MHz due to the addition
08/02/10
1.5
Updated data transfer rate per differential I/O from 1,050 Mb/s to 1,080 Mb/s in
Summary of Spartan-6FPGA Features. Added the -3N speed grade to appropriate section throughout the document,
section with SPI and BPI interface information. Removed the Dynamic Reconfiguration Port section.
Updated the operating speed of the DSP48A1 slice multiplier and accumulator to 390 MHz in
Digital11/05/10
1.6
transceiver data rate to 3.2 Gb/s. Updated the notes in
Figure 1. Added
03/21/11
1.7
Updated from Advance to Preliminary Specification. Removed -4 speed grade from
Summary of10/25/11
2.0
Updated from Preliminary Specification to Production Specification. Updated
Configuration, including
Date
Version
Description of Revisions