- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4236 > XC6SLX150T-2FG676I (Xilinx Inc)IC FPGA SPARTAN 6 676FGGBGA PDF資料下載
參數(shù)資料
| 型號： | XC6SLX150T-2FG676I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 4/89頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SPARTAN 6 676FGGBGA |
| 標準包裝： | 40 |
| 系列： | Spartan® 6 LXT |
| LAB/CLB數(shù)： | 11519 |
| 邏輯元件/單元數(shù)： | 147443 |
| RAM 位總計： | 4939776 |
| 輸入/輸出數(shù)： | 396 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 676-BGA |
| 供應商設備封裝： | 676-FBGA（27x27） |
第1頁第2頁第3頁當前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DS162 (v3.0) October 17, 2011
Product Specification
12
eFUSE Read Endurance
Table 11 lists the minimum guaranteed number of read cycle operations for Device DNA and for the AES eFUSE key. For
more information, see UG380: Spartan-6 FPGA Configuration User Guide.
GTP Transceiver Specifications
GTP transceivers are available in the Spartan-6 LXT devices. See DS160: Spartan-6 Family Overview for more information.
GTP Transceiver DC Characteristics
Table 11: eFUSE Read Endurance
Symbol
Description
Speed Grade
Units
(Min)
-3
-3N
-2
-1L
DNA_CYCLES
Number of DNA_PORT READ operations or JTAG ISC_DNA read
command operations. Unaffected by SHIFT operations.
30,000,000
Read
Cycles
AES_CYCLES
Number of JTAG FUSE_KEY or FUSE_CNTL read command operations.
Unaffected by SHIFT operations.
30,000,000
Read
Cycles
Table 12: Absolute Maximum Ratings for GTP Transceivers(1)
Symbol
Description
MIn
Max
Units
MGTAVCC
Analog supply voltage for the GTP transmitter and receiver circuits relative to
GND
–0.5
1.32
V
MGTAVTTTX
Analog supply voltage for the GTP transmitter termination circuit relative to GND
–0.5
1.32
V
MGTAVTTRX
Analog supply voltage for the GTP receiver termination circuit relative to GND
–0.5
1.32
V
MGTAVCCPLL
Analog supply voltage for the GTP transmitter and receiver PLL circuits relative to
GND
–0.5
1.32
V
MGTAVTTRCAL
Analog supply voltage for the resistor calibration circuit of the GTP transceiver
bank (top or bottom)
–0.5
1.32
V
VIN
Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage
–0.5
1.32
V
VMGTREFCLK
Reference clock absolute input voltage
–0.5
1.32
V
Notes:
1.
Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to
Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
Table 13: Recommended Operating Conditions for GTP Transceivers(1)(2)(3)
Symbol
Description
Min
Typ
Max
Units
MGTAVCC
Analog supply voltage for the GTP transmitter and receiver circuits relative to GND
1.14
1.20
1.26
V
MGTAVTTTX
Analog supply voltage for the GTP transmitter termination circuit relative to GND
1.14
1.20
1.26
V
MGTAVTTRX
Analog supply voltage for the GTP receiver termination circuit relative to GND
1.14
1.20
1.26
V
MGTAVCCPLL
Analog supply voltage for the GTP transmitter and receiver PLL circuits relative to
GND
1.14
1.20
1.26
V
MGTAVTTRCAL
Analog supply voltage for the resistor calibration circuit of the GTP transceiver
bank (top or bottom)
1.14
1.20
1.26
V
Notes:
1.
Each voltage listed requires the filter circuit described in UG386: Spartan-6 FPGA GTP Transceivers User Guide.
2.
Voltages are specified for the temperature range of Tj = –40C to +125C.
3.
The voltage level of MGTAVCCPLL must not exceed the voltage level of MGTAVCC +10mV. The voltage level of MGTAVCC must not exceed the
voltage level of MGTAVCCPLL.
相關PDF資料 |
PDF描述 |
|---|---|
| XC6SLX150T-2FGG900C | IC FPGA SPARTAN 6 147K 900FGGBGA |
| XC6SLX150T-2FGG676I | IC FPGA SPARTAN 6 147K 676FGGBGA |
| ABC60DREH-S734 | CONN EDGECARD 120PS .100 EYELET |
| 24AA65/SM | IC EEPROM 64KBIT 400KHZ 8SOIC |
| XC6SLX150T-3FGG676C | IC FPGA SPARTAN 6 147K 676FGGBGA |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XC6SLX150T-2FG900C | 制造商:Xilinx 功能描述:FPGA SPARTAN?-6 FAMILY 147443 CELLS 45NM (CMOS) TECHNOLOGY 1 - Trays 制造商:Xilinx 功能描述:IC FPGA SPARTAN 6 147K 900BGA |
| XC6SLX150T-2FG900I | 功能描述:IC FPGA SPARTAN 6 900FGGBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan® 6 LXT 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應商設備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XC6SLX150T-2FGG484C | 功能描述:IC FPGA SPARTAN 6 147K 484FGGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan® 6 LXT 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應商設備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XC6SLX150T-2FGG484CES9953 | 制造商:Xilinx 功能描述:XLXXC6SLX150T-2FGG484CES9953 SPARTAN6LXT |
| XC6SLX150T-2FGG484I | 功能描述:IC FPGA SPARTAN 6 147K 484FGGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan® 6 LXT 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應商設備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
發(fā)布緊急采購，3分鐘左右您將得到回復。