參數(shù)資料
型號： XC6SLX150T-2FG676I
廠商： Xilinx Inc
文件頁數(shù)： 59/89頁
文件大?。?/td> 0K
描述： IC FPGA SPARTAN 6 676FGGBGA
標(biāo)準(zhǔn)包裝： 40
系列： Spartan® 6 LXT
LAB/CLB數(shù)： 11519
邏輯元件/單元數(shù)： 147443
RAM 位總計： 4939776
輸入/輸出數(shù)： 396
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 676-BGA
供應(yīng)商設(shè)備封裝： 676-FBGA（27x27）
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DS162 (v3.0) October 17, 2011
Product Specification
62
Table 57: Switching Characteristics for the Digital Frequency Synthesizer DFS (DCM_CLKGEN)(1)
Symbol
Description
Speed Grade
Units
-3
-3N
-2
-1L
Min
Max
Min
Max
Min
Max
Min
Max
Output Frequency Ranges (DCM_CLKGEN)
CLKOUT_FREQ_FX
Frequency for the CLKFX and
CLKFX180 outputs
5
3755375
5333
5
200
MHz
CLKOUT_FREQ_FXDV
Frequency for the CLKFXDV
output
0.15625
187.5 0.15625 187.5 0.15625 166.5 0.15625
100
MHz
Output Clock Jitter(2)(3)
CLKOUT_PER_JITT_FX
Period jitter at the CLKFX and
CLKFX180 outputs.
Typical = ±[0.2% of CLKFX period + 100]
ps
CLKOUT_PER_JITT_FXDV Period jitter at the CLKFXDV
output.
Typical = ±[0.2% of CLKFX period + 100]
ps
CLKFX_FREEZE_VAR
CLKFX period change in free
running oscillator mode at the
same temperature.
FCLKFX > 50 MHz
Maximum = ±3% of CLKFX period
ps
CLKFX period change in free
running oscillator mode at the
same temperature.
FCLKFX < 50 MHz
Maximum = ±5% of CLKFX period
ps
CLKFX_FREEZE_TEMP
_SLOPE
CLKFX period will change in
free_oscillator mode over
temperature. Add to
CLKFX_FREEZE_VAR to
determine total CLKFX period
change. Percentage change for
CLKFX period over 1°C.
Maximum = 0.1
%/°C
Duty Cycle(4)(5)
CLKOUT_DUTY_CYCLE_
FX
Duty cycle precision for the
CLKFX and CLKFX180 outputs,
including the BUFGMUX and
clock tree duty-cycle distortion
Maximum = ±[1% of CLKFX period + 350]
ps
CLKOUT_DUTY_CYCLE_
FXDV
Duty cycle precision for the
CLKFXDV outputs, including the
BUFGMUX and clock tree
duty-cycle distortion
Maximum = ±[1% of CLKFX period + 350]
ps
Lock Time
LOCK_FX(2)
The time from deassertion at the
DCM’s Reset input to the rising
transition at its LOCKED output.
The DFS asserts LOCKED when
the CLKFX, CLKFX180, and
CLKFXDV signals are valid.
Lock time requires
CLKFX_DIVIDE < FIN/(0.50
MHz)
when: FCLKIN <50MHz
–50
–
50
–50–
50
ms
when: FCLKIN > 50 MHz
–5–5–5
–5
ms
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