參數資料
型號： XC6VCX240T-2FFG1156I
廠商： Xilinx Inc
文件頁數： 42/52頁
文件大?。?/td> 0K
描述： IC FPGA VIRTEX 6 241K 1156FFGBGA
產品培訓模塊： Virtex-6 FPGA Overview
產品變化通告： Virtex-6 FIFO Input Logic Reset 18/Apr/2011
標準包裝： 1
系列： Virtex® 6 CXT
LAB/CLB數： 18840
邏輯元件/單元數： 241152
RAM 位總計： 15335424
輸入/輸出數： 600
電源電壓： 0.95 V ~ 1.05 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 1156-BBGA，FCBGA
供應商設備封裝： 1156-FCBGA（35x35）
Virtex-6 CXT Family Data Sheet
DS153 (v1.6) February 11, 2011
Product Specification
47
Virtex-6 CXT Device Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in Table 58. Values are expressed in nanoseconds unless otherwise noted.
Table 58: Global Clock Input to Output Delay Without MMCM
Symbol
Description
Device
Speed Grade
Units
-2
-1
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, without MMCM.
TICKOF
Global Clock input and OUTFF without MMCM
XC6VCX75T
5.88
ns
XC6VCX130T
6.00
ns
XC6VCX195T
6.13
ns
XC6VCX240T
6.13
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
Table 59: Global Clock Input to Output Delay With MMCM
Symbol
Description
Device
Speed Grade
Units
-2
-1
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with MMCM.
TICKOFMMCMGC
Global Clock Input and OUTFF with MMCM
XC6VCX75T
2.77
ns
XC6VCX130T
2.78
ns
XC6VCX195T
2.78
ns
XC6VCX240T
2.79
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2.
MMCM output jitter is already included in the timing calculation.
Table 60: Clock-Capable Clock Input to Output Delay With MMCM
Symbol
Description
Device
Speed Grade
Units
-2
-1
LVCMOS25 Clock-capable Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with MMCM.
TICKOFMMCMCC
Clock-capable Clock Input and OUTFF with
MMCM
XC6VCX75T
2.63
ns
XC6VCX130T
2.65
ns
XC6VCX195T
2.65
ns
XC6VCX240T
2.65
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2.
MMCM output jitter is already included in the timing calculation.
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相關代理商/技術參數
參數描述
XC6VCX240T-2FFG784C 功能描述:IC FPGA VIRTEX 6 241K 784FFGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:Virtex® 6 CXT 產品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數:4080 邏輯元件/單元數:52224 RAM 位總計:4866048 輸入/輸出數:480 門數:- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，FCBGA 供應商設備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XC6VCX240T-2FFG784I 功能描述:IC FPGA VIRTEX 6 241K 784FFGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:Virtex® 6 CXT 產品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數:100 邏輯元件/單元數:238 RAM 位總計:3200 輸入/輸出數:80 門數:3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應商設備封裝:120-CPGA（34.55x34.55）
XC6VCX75T 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-6 CXT Family Data Sheet
XC6VCX75T-1FF484C 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 74496 CELLS 40NM (CMOS) TECHNOLOGY - Trays 制造商:Xilinx 功能描述:IC FPGA VIRTEX 6 75K 484BGA
XC6VCX75T-1FF484I 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 74496 CELLS 40NM (CMOS) TECHNOLOGY - Trays 制造商:Xilinx 功能描述:IC FPGA 240 I/O 484FCBGA
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