參數(shù)資料
型號(hào)： XC6VCX75T-1FFG784I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 33/52頁(yè)
文件大?。?/td> 0K
描述： IC FPGA VIRTEX 6 74K 784FFGBGA
產(chǎn)品培訓(xùn)模塊： Virtex-6 FPGA Overview
產(chǎn)品變化通告： Virtex-6 FIFO Input Logic Reset 18/Apr/2011
標(biāo)準(zhǔn)包裝： 1
系列： Virtex® 6 CXT
LAB/CLB數(shù)： 5820
邏輯元件/單元數(shù)： 74496
RAM 位總計(jì)： 5750784
輸入/輸出數(shù)： 360
電源電壓： 0.95 V ~ 1.05 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 784-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 784-FCBGA
Virtex-6 CXT Family Data Sheet
DS153 (v1.6) February 11, 2011
Product Specification
39
DSP48E1 Switching Characteristics
Table 51: DSP48E1 Switching Characteristics
Symbol
Description
Speed Grade
Units
-2
-1
Setup and Hold Times of Data/Control Pins to the Input Register Clock
TDSPDCK_{A, ACIN; B, BCIN}_{AREG; BREG}/
TDSPCKD_{A, ACIN; B, BCIN}_{AREG; BREG}
{A, ACIN, B, BCIN} input to {A, B} register CLK
0.35/0.34
0.41/0.39
ns
TDSPDCK_C_CREG/TDSPCKD_C_CREG
C input to C register CLK
0.22/0.24
0.26/0.27
ns
TDSPDCK_D_DREG/TDSPCKD_D_DREG
D input to D register CLK
0.15/0.39
0.17/0.44
ns
Setup and Hold Times of Data Pins to the Pipeline Register Clock
TDSPDCK_{A, ACIN, B, BCIN}_PREG_MULT/
TDSPCKD_{A, ACIN, B, BCIN}_PREG_MULT
{A, ACIN, B, BCIN} input to M register CLK
3.21/0.02
3.69/0.02
ns
TDSPDCK_{A, D}_ADREG/ TDSPCKD_{A, D}_ADREG
{A, D} input to AD register CLK
1.69/0.13
1.94/0.15
ns
Setup and Hold Times of Data/Control Pins to the Output Register Clock
TDSPDCK_{A, ACIN, B, BCIN}_PREG_MULT/
TDSPCKD_{A, ACIN, B, BCIN}_PREG_MULT
{A, ACIN, B, BCIN} input to P register CLK using
multiplier
5.20/–0.19
5.97/–0.22
ns
TDSPDCK_D_DREG_MULT/ TDSPCKD_D_DREG_MULT
D input to P register CLK
4.90/–0.65
5.63/–0.75
ns
TDSPDCK_{A, ACIN, B, BCIN}_PREG/
TDSPCKD_{A, ACIN, B, BCIN}_PREG
{A, ACIN, B, BCIN} input to P register CLK not
using multiplier
2.15/–0.19
2.47/–0.22
ns
TDSPDCK_C_PREG/ TDSPCKD_C_PREG
C input to P register CLK
1.91/–0.14
2.19/–0.17
ns
TDSPDCK_{PCIN, CARRYCASCIN, MULTSIGNIN}_PREG/
TDSPCKD_{PCIN, CARRYCASCIN, MULTSIGNIN}_PREG
{PCIN, CARRYCASCIN, MULTSIGNIN} input to
P register CLK
1.67/–0.04
1.92/–0.05
ns
Setup and Hold Times of the CE Pins
TDSPDCK_{CEA; CEB}_{AREG; BREG}/
TDSPCKD_{CEA; CEB}_{AREG; BREG}
{CEA; CEB} input to {A; B} register CLK
0.22/0.25
0.25/0.29
ns
TDSPDCK_CEC_CREG/ TDSPCKD_CEC_CREG
CEC input to C register CLK
0.24/0.23
0.28/0.27
ns
TDSPDCK_CED_DREG/ TDSPCKD_CED_DREG
CED input to D register CLK
0.31/0.14
0.35/0.16
ns
TDSPDCK_CEM_MREG/ TDSPCKD_CEM_MREG
CEM input to M register CLK
0.26/0.25
0.30/0.28
ns
TDSPDCK_CEP_PREG/ TDSPCKD_CEP_PREG
CEP input to P register CLK
0.46/0.03
0.53/0.03
ns
Setup and Hold Times of the RST Pins
TDSPDCK_{RSTA; RSTB}_{AREG; BREG}/
TDSPCKD_{RSTA; RSTB}_{AREG; BREG}
{RSTA, RSTB} input to {A, B} register CLK
0.38/0.22
0.43/0.25
ns
TDSPDCK_RSTC_CREG/ TDSPCKD_RSTC_CREG
RSTC input to C register CLK
0.23/0.09
0.27/0.11
ns
TDSPDCK_RSTD_DREG/ TDSPCKD_RSTD_DREG
RSTD input to D register CLK
0.38/0.19
0.44/0.21
ns
TDSPDCK_RSTM_MREG/ TDSPCKD_RSTM_MREG
RSTM input to M register CLK
0.26/0.30
0.30/0.35
ns
TDSPDCK_RSTP_PREG/ TDSPCKD_RSTP_PREG
RSTP input to P register CLK
0.33/0.05
0.41/0.06
ns
Combinatorial Delays from Input Pins to Output Pins
TDSPDO_{A, B}_{P, CARRYOUT}_MULT
{A, B} input to {P, CARRYOUT} output using
multiplier
5.08
5.84
ns
TDSPDO_D_{P, CARRYOUT}_MULT
D input to {P, CARRYOUT} output using
multiplier
4.82
5.54
ns
TDSPDO_{A, B}_{P, CARRYOUT}
{A, B} input to {P, CARRYOUT} output not using
multiplier
2.07
2.38
ns
TDSPDO_{C, CARRYIN}_{P, CARRYOUT}
{C, CARRYIN} input to {P, CARRYOUT} output
1.83
2.10
ns
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參數(shù)描述
XC6VCX75T-2FF484C 制造商:Xilinx 功能描述:IC FPGA VIRTEX 6 75K 484BGA
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XC6VCX75T-2FF784C 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 74496 CELLS 40NM (CMOS) TECHNOLOGY - Trays 制造商:Xilinx 功能描述:IC FPGA 360 I/O 784FCBGA
XC6VCX75T-2FF784I 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 74496 CELLS 40NM (CMOS) TECHNOLOGY - Trays 制造商:Xilinx 功能描述:IC FPGA VIRTEX 6 75K 784BGA
XC6VCX75T-2FFG484C 功能描述:IC FPGA VIRTEX 6 74K 484FFGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Virtex® 6 CXT 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
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