參數(shù)資料
型號(hào)： XC7K420T-3FFG901E
廠商： XILINX INC
元件分類： FPGA
英文描述： FPGA, PBGA900
封裝： LEAD FREE, FBGA-900
文件頁(yè)數(shù)： 17/50頁(yè)
文件大?。?/td> 1218K
代理商： XC7K420T-3FFG901E
Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics
DS182 (v1.1) April 1, 2011
Advance Product Specification
24
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 28 shows the test setup parameters used for measuring input delay.
Table 28: Input Delay Measurement Methodology
Description
I
/O Standard Attribute
VMEAS
VREF
LVTTL
0
3.3
1.65
–
LVCMOS, 3.3V
LVCMOS33
0
3.3
1.65
–
LVCMOS, 2.5V
LVCMOS25
0
2.5
1.25
–
LVCMOS, 1.8V
LVCMOS18
0
1.8
0.9
–
LVCMOS, 1.5V
LVCMOS15
0
1.5
0.75
–
HSTL (High-Speed Transceiver Logic),
Class I & II
HSTL_I, HSTL_II
VREF –0.5
VREF +0.5
VREF
0.75
HSTL, Class I & II, 1.8V
HSTL_I_18, HSTL_II_18
VREF –0.5
VREF +0.5
VREF
0.90
SSTL (Stub Terminated Transceiver Logic),
1.5V and 1.35V
SSTL15, SSTL135
VREF –1.00
VREF +1.00
VREF
0.75,
0.675
SSTL, Class I & II, 1.8V
SSTL18_I, SSTL18_II
VREF –0.5
VREF +0.5
VREF
0.90
LVDS (Low-Voltage Differential Signaling), HR I/O Banks LVDS_25
1.2 – 0.125
1.2 + 0.125
–
LVDS (Low-Voltage Differential Signaling), HP I/O Banks LVDS
1.2 – 0.125
1.2 + 0.125
–
Notes:
1.
The input delay measurement methodology parameters for LVDCI are the same for LVCMOS standards of the same voltage. Input delay
measurement methodology parameters for HSLVDCI are the same as for HSTL_II standards of the same voltage. Parameters for all other DCI
standards are the same for the corresponding non-DCI standards.
2.
Input waveform switches between VLand VH.
3.
Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF
values listed are typical.
4.
Input voltage level from which measurement starts.
5.
This is an input voltage reference that bears no relation to the VREF / VMEAS parameters found in IBIS models and/or noted in Figure 4.
6.
The value given is the differential input voltage.
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