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| 型號(hào)： | XC7K420T-3FFG901E |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | FPGA, PBGA900 |
| 封裝： | LEAD FREE, FBGA-900 |
| 文件頁(yè)數(shù)： | 3/50頁(yè) |
| 文件大小： | 1218K |
| 代理商： | XC7K420T-3FFG901E |
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Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics
DS182 (v1.1) April 1, 2011
Advance Product Specification
11
XADC Specifications
Table 19: XADC Specifications
Parameter
Symbol
Comments/Conditions
Min
Typ
Max
Units
VCCADC = 1.8V ± 5%, VREFP =1.25V, VREFN = 0V, ADCCLK = 26 MHz, Tj = –40°C to 100°C, Typical values at Tj=+40°C
ADC Accuracy(1)
Resolution
12
–
Bits
Integral Nonlinearity
INL
–
±2
LSBs
Differential Nonlinearity
DNL
No missing codes, guaranteed monotonic
–
±1
LSBs
Offset Error
Calibrated
–
±4
LSBs
Gain Error
Calibrated
–
±0.4
%
Channel Matching
Based on two individual ADC instances with
calibration enabled
–
10
LSBs
Sample Rate
0.1
–
1
MS/s
Signal to Noise Ratio
SNR
FSAMPLE = 500KS/s, FIN = 20KHz
60
–
dB
RMS Code Noise
External 1.25V reference
–
2
LSBs
On-chip reference
–
3
–
LSBs
Total Harmonic Distortion
THD
FSAMPLE = 500KS/s, FIN = 20KHz
75
–
dB
ADC Accuracy at Extended Temperatures (-55°C to 125°C)
Resolution
10
–
Bits
Integral Nonlinearity
INL
–
±1
LSB
(at 10 bits)
Differential Nonlinearity
DNL
No missing codes, guaranteed monotonic
–
±1
Analog Inputs(2)
ADC Input Ranges
Unipolar operation
0
–
1
V
Bipolar operation
–0.5
–
+0.5
V
Unipolar common mode range (FS input)
0
–
+0.5
V
Bipolar common mode range (FS input)
+0.5
–
+0.6
V
Maximum External Channel
Input Ranges
Adjacent channels set within these ranges
should not corrupt measurements on adjacent
channels
–0.1
–
VCCADC
V
Auxiliary Channel Full
Resolution Bandwidth
FRBW
250
–
KHz
On-Chip Sensors
Temperature Sensor Error
Tj = –40°C to 100°C.
–
±4
°C
Tj = –55°C to +125°C
–
±6
°C
Supply Sensor Error
Measurement range of VCCAUX 1.8V ±5%
Tj = –40°C to +100°C
––
±1
%
Measurement range of VCCAUX 1.8V ±5%
Tj = –55°C to +125°C
––
±2
%
Conversion Rate(3)
Conversion Time - Continuous
tCONV
Number of ADCCLK cycles
26
–
32
Conversion Time - Event
tCONV
Number of CLK cycles
–
21
DRP Clock Frequency
DCLK
DRP clock frequency
8
–
250
MHz
ADC Clock Frequency
ADCCLK
Derived from DCLK
1
–
26
MHz
DCLK Duty Cycle
40
–
60
%
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