參數(shù)資料
型號(hào): XCF04SVOG20C
廠商: Xilinx Inc
文件頁(yè)數(shù): 8/35頁(yè)
文件大小: 0K
描述: IC PROM SRL FOR 4M GATE 20-TSSOP
標(biāo)準(zhǔn)包裝: 74
可編程類型: 系統(tǒng)內(nèi)可編程
存儲(chǔ)容量: 4Mb
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 管件
產(chǎn)品目錄頁(yè)面: 601 (CN2011-ZH PDF)
其它名稱: 122-1288-5
Platform Flash In-System Programmable Configuration PROMs
DS123 (v2.18) May 19, 2010
Product Specification
16
R
AC Electrical Characteristics
AC Characteristics Over Operating Conditions
XCFxxS and XCFxxP PROM as Configuration Slave with CLK Input Pin as Clock Source
X-Ref Target - Figure 7
Symbol
Description
XCF01S, XCF02S,
XCF04S
XCF08P, XCF16P,
XCF32P
Units
Min
Max
Min
Max
THCF
CF hold time to guarantee design revision selection is
sampled when VCCO = 3.3V or 2.5V(9)
300
ns
CF hold time to guarantee design revision selection is
sampled when VCCO = 1.8V(9)
300
ns
TCF
CF to data delay when VCCO = 3.3V or 2.5V(8)
–––
25
ns
CF to data delay when VCCO = 1.8V(8)
–––
25
ns
TOE
OE/RESET to data delay(6) when VCCO = 3.3V or 2.5V
10
25
ns
OE/RESET to data delay(6) when VCCO = 1.8V
–30–25
ns
TCE
CE to data delay(5) when VCCO = 3.3V or 2.5V
15
25
ns
CE to data delay(5) when VCCO = 1.8V
–30–25
ns
TCAC
CLK to data delay(7) when VCCO = 3.3V or 2.5V
15
25
ns
CLK to data delay(7) when VCCO = 1.8V
–30–25
ns
TOH
Data hold from CE, OE/RESET, CLK, or CF
when VCCO = 3.3V or 2.5V(8)
0–5–
ns
Data hold from CE, OE/RESET, CLK, or CF
when VCCO = 1.8V(8)
0–5–
ns
TDF
CE or OE/RESET to data float delay(2)
when VCCO = 3.3V or 2.5V
–25–45
ns
CE or OE/RESET to data float delay(2)
when VCCO = 1.8V
–30–45
ns
CE
OE/RESET
CLK
BUSY
(optional)
DATA
TCE
TLC
THC
TSCE
TOE
TCAC
THCE
THOE
TCYC
TOH
TDF
TOH
THB
TSB
CF
EN_EXT_SEL
REV_SEL[1:0]
TSXT
THXT
TSRV
THRV
ds123_22_122905
TSXT
THXT
TSRV
THRV
TCF
THCF
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