參數(shù)資料
型號(hào)： XCF32PFS48C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 26/35頁(yè)
文件大小： 0K
描述： IC PROM SRL 1.8V 32M 48CSBGA
標(biāo)準(zhǔn)包裝： 108
可編程類型： 系統(tǒng)內(nèi)可編程
存儲(chǔ)容量： 32Mb
電源電壓： 1.65 V ~ 2 V
工作溫度： -40°C ~ 85°C
封裝/外殼： 48-BFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 48-CSP（8x9）
包裝： 托盤
Platform Flash In-System Programmable Configuration PROMs
DS123 (v2.18) May 19, 2010
Product Specification
32
R
Revision History
The following table shows the revision history for this document.
Date
Version
Revision
04/29/03
1.0
Xilinx Initial Release.
06/03/03
1.1
Made edits to all pages.
11/05/03
2.0
Major revision.
11/18/03
2.1
Pinout corrections as follows:
For VO48 package, removed 38 from VCCINT and added it to VCCO.
For FS48 package, removed pin D6 from VCCINT and added it to VCCO.
Table 14 (FS48 package):
For pin D6, changed name from VCCINT to VCCO.
For pin A4, changed name from GND to DNC.
Figure 8 (VO48 package): For pin 38, changed name from VCCINT to VCCO.
12/15/03
2.2
Added specification (4.7k
Ω) for recommended pull-up resistor on OE/RESET pin to section
Added paragraph to section "Standby Mode," page 12, concerning use of a pull-up resistor
and/or buffer on the DONE pin.
05/07/04
2.3
Section "Features," page 1: Added package styles and 33 MHz configuration speed limit to
itemized features.
Section "Description," page 1 and following: Added state conditions for CF and BUSY to the
descriptive text.
Table 2, page 3: Updated Virtex-II configuration bitstream sizes.
Section "Design Revisioning," page 8: Rewritten.
Section "Initiating FPGA Configuration," page 10 and following, five instances: Added instruction
to tie CF High if it is not tied to the FPGA’s PROG_B (PROGRAM) input.
Figure 6, page 16, through Figure 13, page 23: Added footnote indicating the directionality of the
CF pin in each configuration.
Table 12, page 25: Added CF column to truth table, and added an additional row to document
the Low state of CF.
Section "Absolute Maximum Ratings," page 13: Revised VIN and VTS for ’P’ devices.
Revised footnote callout number on TOER from Footnote (4) to Footnote (3).
Added Footnote (2) callout to TVCC.
Added Typical (Typ) parameter columns and parameters for VCCINT and VCCO/VCCJ.
Added 1.5V operation parameter row to VIL and VIH, ’P’ devices.
Revised VIH Min, 2.5V operation, from 2.0V to 1.7V.
Added parameter row TIN and Max parameters
(Continued on next page)
Added parameter row and parameters for parallel configuration mode, ’P’ devices, to ICCO.
Added Footnote (1) and Footnote (2) with callouts in the Test Conditions column for ICCJ,
ICCINTS, ICCOS, and ICCJS, to define active and standby mode requirements.
Corrected description for second TCAC parameter line to show parameters for 1.8V VCCO.
Revised Footnote (7) to indicate VCCO = 3.3V.
Applied Footnote (7) to second TCYC parameter line.
Footnote (5)TCYC Min and TCAC Min formulas.
Table 14, page 39:
Added additional state conditions to CLK description.
Added function of resetting the internal address counter to CF description.
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