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參數(shù)資料
| 型號： | XCR3064XL-6CS48C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ISP CPLD 64 MCELL 3.3V 48-CSP |
| 標(biāo)準(zhǔn)包裝： | 416 |
| 系列： | CoolRunner XPLA3 |
| 可編程類型： | 系統(tǒng)內(nèi)可編程（最少 1K 次編程/擦除循環(huán)） |
| 最大延遲時間 tpd(1)： | 5.5ns |
| 電壓電源 - 內(nèi)部： | 3 V ~ 3.6 V |
| 邏輯元件/邏輯塊數(shù)目： | 4 |
| 宏單元數(shù)： | 64 |
| 門數(shù)： | 1500 |
| 輸入/輸出數(shù)： | 40 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-FBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 48-CSBGA（7x7） |
| 包裝： | 托盤 |
CoolRunner XPLA3 CPLD
8
DS012 (v2.5) May 26, 2009
Product Specification
R
3V, In-System Programming (ISP)
CoolRunner XPLA3 CPLDs allow for 3V, in-system pro-
gramming/reprogramming of its EEPROM cells via a JTAG
interface. An on-chip charge pump eliminates the need for
externally provided super-voltages. This allows program-
ming on the circuit board using only the 3V supply required
by the device for normal operation. The ISP commands
implemented in CoolRunner XPLA3 CPLDs are specified in
Table 4: XPLA3 Low-level JTAG Boundary-scan Commands
Instruction
(Instruction
Code)
Register Used
Description
Sample/Preload
(00010)
Boundary-scan
Register
The mandatory Sample/Preload instruction allows a snapshot of the normal operation of the
component to be taken and examined. It also allows data values to be loaded into the latched parallel
outputs of the Boundary-scan Shift Register prior to selection of the other boundary-scan test
instructions.
Extest
(00000)
Boundary-scan
Register
The mandatory Extest instruction allows testing of off-chip circuitry and board level interconnections.
Data is typically loaded onto the latched parallel outputs of Boundary-scan Shift Register using the
Sample/Preload instruction prior to selection of the Extest instruction.
Bypass
(11111)
Bypass Register
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass
synchronously through the selected device to adjacent devices during normal device operation. The
Bypass instruction can be entered by holding TDI at a constant High value and completing an
Instruction-scan cycle.
Idcode
(00001)
Boundary-scan
Register
Selects the Idcode register and places it between TDI and TDO, allowing the Idcode to be serially
shifted out of TDO. The Idcode instruction permits blind interrogation of the components assembled
onto a printed circuit board. Thus, in circumstances where the component population can vary, it is
possible to determine what components exist in a product.
High-Z
(00101)
Bypass Register
The High-Z instruction places the component in a state which all of its system logic outputs are placed
in an inactive drive state (e.g., high impedance). In this state, an in-circuit test system can drive
signals onto the connections normally driven by a component output without incurring the risk of
damage to the component. The High-Z instruction also forces the Bypass Register between TDI and
TDO.
Intest
(00011)
Boundary-scan
Register
The Intest instruction selects the boundary scan register prior to applying tests to the logic core of the
device. This permits testing of on-chip system logic while the component is already on the board.
Table 5: JTAG Pin Description
Pin
Name
Description
TCK
Test Clock Input
Clock pin to shift the serial data and instructions in and out of the TDI and TDO pins,
respectively.
TMS
Test Mode Select
Serial input pin selects the JTAG instruction mode. TMS should be driven High during
user mode operation.
TDI
Test Data Input
Serial input pin for instructions and test data. Data is shifted in on the rising edge of
TCK.
TDO
Test Data Output
Serial output pin for instructions and test data. Data is shifted out on the falling edge
of TCK. The signal is 3-stated if data is not being shifted out of the device.
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