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參數(shù)資料
| 型號： | XA2C128-7VQG100I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 1/16頁 |
| 文件大小： | 0K |
| 描述： | IC CPLD 128MCELL 80 I/O 100VQFP |
| 產(chǎn)品培訓模塊： | CoolRunner-II CPLD Starter Kit |
| 標準包裝： | 90 |
| 系列： | CoolRunner II |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時間 tpd(1)： | 7.0ns |
| 電壓電源 - 內(nèi)部： | 1.7 V ~ 1.9 V |
| 邏輯元件/邏輯塊數(shù)目： | 8 |
| 宏單元數(shù)： | 128 |
| 門數(shù)： | 3000 |
| 輸入/輸出數(shù)： | 80 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP |
| 供應商設(shè)備封裝： | 100-VQFP（14x14） |
| 包裝： | 托盤 |
DS554 (v1.2) June 9, 2009
Product Specification
1
2006–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. All other trademarks are the property of their respective owners.
Features
AEC-Q100 device qualification and full PPAP support
available in both I-grade and extended temperature
Q-grade
Guaranteed to meet full electrical specifications over
TA = –40°C to +105°C with TJ Maximum = +125°C
(Q-grade)
Optimized for 1.8V systems
Industry’s best 0.18 micron CMOS CPLD
-
Optimized architecture for effective logic synthesis
-
Multi-voltage I/O operation — 1.5V to 3.3V
Available in the following package options
-
100-pin VQFP with 80 user I/O
-
132-ball CP (0.5 mm) BGA with 100 user I/O
-
Pb-free only for all packages
Advanced system features
-
Fastest in system programming
1.8V ISP using IEEE 1532 (JTAG) interface
-
IEEE1149.1 JTAG Boundary Scan Test
-
Optional Schmitt-trigger input (per pin)
-
Unsurpassed low power management
DataGATE enable (DGE) signal control
-
Two separate I/O banks
-
RealDigital 100% CMOS product term generation
-
Flexible clocking modes
Optional DualEDGE triggered registers
Clock divider (divide by 2,4,6,8,10,12,14,16)
CoolCLOCK
-
Global signal options with macrocell control
Multiple global clocks with phase selection per
macrocell
Multiple global output enables
Global set/reset
-
Advanced design security
-
Open-drain output option for Wired-OR and LED
drive
-
PLA architecture
Superior pinout retention
100% product term routability across function
block
-
Optional bus-hold, 3-state or weak pull-up on
selected I/O pins
-
Optional configurable grounds on unused I/Os
-
Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels
-
Hot pluggable
Refer to the CoolRunner-II Automotive CPLD family data
sheet for architecture description.
WARNING: Programming temperature range of
TA = 0° C to +70° C.
Description
The CoolRunner-II Automotive 128-macrocell device is
designed for both high performance and low power applica-
tions. This lends power savings to high-end communication
equipment and high speed to battery operated devices. Due
to the low power stand-by and dynamic operation, overall
system reliability is improved.
This device consists of eight Function Blocks inter-con-
nected by a low power Advanced Interconnect Matrix (AIM).
The AIM feeds 40 true and complement inputs to each
Function Block. The Function Blocks consist of a 40 by 56
P-term PLA and 16 macrocells which contain numerous
configuration bits that allow for combinational or registered
modes of operation.
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain and programmable grounds. A Schmitt-trigger
input is available on a per input pin basis. In addition to stor-
ing macrocell output states, the macrocell registers may be
configured as direct input registers to store signals directly
from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as a
synchronous clock source. Macrocell registers can be indi-
vidually configured to power up to the zero or one state. A
global set/reset control line is also available to asynchro-
nously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchro-
nous set/reset and output enable signals can be formed
using product terms on a per-macrocell or per-Function
Block basis.
A DualEDGE flip-flop feature is also available on a per mac-
rocell basis. This feature allows high performance synchro-
nous operation based on lower frequency clocking to help
reduce the total power consumption of the device.
Circuitry has also been included to divide one externally
supplied global clock (GCK2) by eight different selections.
This yields divide by even and odd clock frequencies.
0
XA2C128 CoolRunner-II
Automotive CPLD
DS554 (v1.2) June 9, 2009
00
Product Specification
R
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| XA2C128-8CPG132Q | 功能描述:IC CPLD 128MC 100 I/O 132CSBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - CPLD（復雜可編程邏輯器件） 系列:CoolRunner II 標準包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤 |
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