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| 型號： | XCS30XL-5TQ100I |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達和Spartan - xL的家庭現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 38/82頁 |
| 文件大?。?/td> | 863K |
| 代理商： | XCS30XL-5TQ100I |
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
DS060 (v1.6) September 19, 2001
Product Specification
1-800-255-7778
R
Spartan DC Characteristics Over Operating Conditions
Spartan Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values where one global clock input
drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by
the global clock net.
When fewer vertical clock lines are connected, the clock dis-
tribution is faster; when multiple clock lines per column are
driven from the same global clock, the delay is longer. For
more specific, more precise, and worst-case guaranteed
data, reflecting the actual routing structure, use the values
provided by the static timing analyzer (TRCE in the Xilinx
Development System) and back-annotated to the simulation
netlist. These path delays, provided as a guideline, have
been extracted from the static timing analyzer report. All
timing parameters assume worst-case operating conditions
(supply voltage and junction temperature).
Symbol
Description
Min
Max
Units
VOH
High-level output voltage @ IOH = –4.0 mA, VCC min
TTL outputs
2.4
-
V
High-level output voltage @ IOH = –1.0 mA, VCC min
CMOS outputs
VCC – 0.5
-
V
VOL
Low-level output voltage @ IOL = 12.0 mA, VCC min(1)
TTL outputs
-
0.4
V
CMOS outputs
-
0.4
V
VDR
Data retention supply voltage (below which configuration data may be lost)
3.0
-
V
ICCO
Quiescent FPGA supply current(2)
Commercial
-
3.0
mA
Industrial
-
6.0
mA
IL
Input or output leakage current
–10
+10
A
CIN
Input capacitance (sample tested)
-
10
pF
IRPU
Pad pull-up (when selected) @ VIN = 0V (sample tested)
0.02
0.25
mA
IRPD
Pad pull-down (when selected) @ VIN = 5V (sample tested)
0.02
-
mA
Notes:
1.
With 50% of the outputs simultaneously sinking 12 mA, up to a maximum of 64 pins.
2.
With no output current loads, no active input pull-up resistors, all package pins at VCC or GND, and the FPGA configured with a Tie
option.
Symbol
Description
Device
Speed Grade
Units
-4
-3
Max
TPG
From pad through Primary buffer, to any clock K
XCS05
2.0
4.0
ns
XCS10
2.4
4.3
ns
XCS20
2.8
5.4
ns
XCS30
3.2
5.8
ns
XCS40
3.5
6.4
ns
TSG
From pad through Secondary buffer, to any clock K
XCS05
2.5
4.4
ns
XCS10
2.9
4.7
ns
XCS20
3.3
5.8
ns
XCS30
3.6
6.2
ns
XCS40
3.9
6.7
ns
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PDF描述 |
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| XCS30XL-5TQ144I | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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| XCS40XL-5PQ100I | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XCS30XL-5TQ144C | 功能描述:IC FPGA 3.3V C-TEMP HP 144TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-XL 標準包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應商設備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XCS30XL-5TQ144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL FPGA |
| XCS30XL-5TQ208C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS30XL-5TQ208I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS30XL-5TQ240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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