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參數(shù)資料
| 型號： | XCS40XL-4PQ208C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 60/83頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 3.3V C-TEMP 208-PQFP |
| 產(chǎn)品變化通告： | Product Discontinuation 26/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | Spartan®-XL |
| LAB/CLB數(shù)： | 784 |
| 邏輯元件/單元數(shù)： | 1862 |
| RAM 位總計(jì)： | 25088 |
| 輸入/輸出數(shù)： | 169 |
| 門數(shù)： | 40000 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-PQFP（28x28） |
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Spartan and Spartan-XL FPGA Families Data Sheet
DS060 (v2.0) March 1, 2013
63
Product Specification
R
Product Obsolete/Under Obsolescence
PWRDWN
II
PWRDWN is an active Low input that forces the FPGA into the Power Down state
and reduces power consumption. When PWRDWN is Low, the FPGA disables all
I/O and initializes all flip-flops. All inputs are interpreted as Low independent of
their actual level. VCC must be maintained, and the configuration data is
maintained. PWRDWN halts configuration if asserted before or during
configuration, and re-starts configuration when removed. When PWRDWN returns
High, the FPGA becomes operational by first enabling the inputs and flip-flops and
then enabling the outputs. PWRDWN has a default internal pull-up resistor.
User I/O Pins That Can Have Special Functions
TDO
O
If boundary scan is used, this pin is the Test Data Output. If boundary scan is not
used, this pin is a 3-state output without a register, after configuration is
completed.
To use this pin, place the library component TDO instead of the usual pad symbol.
An output buffer must still be used.
TDI, TCK,
TMS
II/O
or I
(JTAG)
If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode
Select inputs respectively. They come directly from the pads, bypassing the IOBs.
These pins can also be used as inputs to the CLB logic after configuration is
completed.
If the BSCAN symbol is not placed in the design, all boundary scan functions are
inhibited once configuration is completed, and these pins become
user-programmable I/O. In this case, they must be called out by special library
elements. To use these pins, place the library components TDI, TCK, and TMS
instead of the usual pad symbols. Input or output buffers must still be used.
HDC
O
I/O
High During Configuration (HDC) is driven High until the I/O go active. It is
available as a control output indicating that configuration is not yet completed.
After configuration, HDC is a user-programmable I/O pin.
LDC
O
I/O
Low During Configuration (LDC) is driven Low until the I/O go active. It is available
as a control output indicating that configuration is not yet completed. After
configuration, LDC is a user-programmable I/O pin.
INIT
I/O
Before and during configuration, INIT is a bidirectional signal. A 1 k
Ω to 10 kΩ
external pull-up resistor is recommended.
As an active Low open-drain output, INIT is held Low during the power stabilization
and internal clearing of the configuration memory. As an active Low input, it can
be used to hold the FPGA in the internal WAIT state before the start of
configuration. Master mode devices stay in a WAIT state an additional 30 to
300
μs after INIT has gone High.
During configuration, a Low on this output indicates that a configuration data error
has occurred. After the I/O go active, INIT is a user-programmable I/O pin.
PGCK1 -
PGCK4
(Spartan)
Weak
Pull-up
I or I/O
Four Primary Global inputs each drive a dedicated internal global net with short
delay and minimal skew. If not used to drive a global buffer, any of these pins is a
user-programmable I/O.
The PGCK1-PGCK4 pins drive the four Primary Global Buffers. Any input pad
symbol connected directly to the input of a BUFGP symbol is automatically placed
on one of these pins.
Table 18: Pin Descriptions (Continued)
Pin Name
I/O
During
Config.
I/O After
Config.
Pin Description
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| AMC49DRTS | CONN EDGECARD 98POS .100 DIP SLD |
| XCS40XL-4CS280C | IC FPGA 3.3V C-TEMP 280-CSBGA |
| XCS40XL-4BG256I | IC FPGA 3.3V I-TEMP 256-PBGA |
| AMC49DRES | CONN EDGECARD 98POS .100 EYELET |
| XCS40XL-4BG256C | IC FPGA 3.3V C-TEMP 256-PBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCS40XL-4PQ208I | 功能描述:IC FPGA 3.3V I-TEMP 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-XL 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XCS40XL-4PQ240C | 功能描述:IC 3.3V FPGA COMM. TEMP 240PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-XL 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| XCS40XL-4PQ240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS40XL-4PQ256C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS40XL-4PQ256I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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