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| 型號： | XCV400E-6BG560I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 24/233頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 1.8V I-TEMP 560-MBGA |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標準包裝： | 1 |
| 系列： | Virtex®-E |
| LAB/CLB數(shù)： | 2400 |
| 邏輯元件/單元數(shù)： | 10800 |
| RAM 位總計： | 163840 |
| 輸入/輸出數(shù)： | 404 |
| 門數(shù)： | 569952 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 560-LBGA，金屬 |
| 供應商設備封裝： | 560-MBGA（42.5x42.5） |
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Virtex-E 1.8 V Field Programmable Gate Arrays
R
Module 2 of 4
DS022-2 (v3.0) March 21, 2014
6
Production Product Specification
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Table 5 shows the depth and width aspect ratios for the
block SelectRAM. The Virtex-E block SelectRAM also
includes dedicated routing to provide an efficient interface
with both CLBs and other block SelectRAMs. Refer to
XAPP130 for block SelectRAM timing waveforms.
Programmable Routing Matrix
It is the longest delay path that limits the speed of any
worst-case design. Consequently, the Virtex-E routing
architecture and its place-and-route software were defined
in a joint optimization process. This joint optimization mini-
mizes long-path delays, and consequently, yields the best
system performance.
The joint optimization also reduces design compilation
times because the architecture is software-friendly. Design
cycles are correspondingly reduced due to shorter design
iteration times.
Local Routing
The VersaBlock provides local routing resources (see
Figure 7), providing three types of connections:
Interconnections among the LUTs, flip-flops, and GRM
Internal CLB feedback paths that provide high-speed
connections to LUTs within the same CLB, chaining
them together with minimal routing delay
Direct paths that provide high-speed connections
between horizontally adjacent CLBs, eliminating the
delay of the GRM.
General Purpose Routing
Most Virtex-E signals are routed on the general purpose
routing, and consequently, the majority of interconnect
resources are associated with this level of the routing hier-
archy. General-purpose routing resources are located in
horizontal and vertical routing channels associated with the
CLB rows and columns and are as follows:
Adjacent to each CLB is a General Routing Matrix
(GRM). The GRM is the switch matrix through which
horizontal and vertical routing resources connect, and
is also the means by which the CLB gains access to
the general purpose routing.
24 single-length lines route GRM signals to adjacent
GRMs in each of the four directions.
72 buffered Hex lines route GRM signals to another
GRMs six-blocks away in each one of the four
directions. Organized in a staggered pattern, Hex lines
are driven only at their endpoints. Hex-line signals can
be accessed either at the endpoints or at the midpoint
(three blocks from the source). One third of the Hex
lines are bidirectional, while the remaining ones are
uni-directional.
12 Longlines are buffered, bidirectional wires that
distribute signals across the device quickly and
efficiently. Vertical Longlines span the full height of the
device, and horizontal ones span the full width of the
device.
I/O Routing
Virtex-E devices have additional routing resources around
their periphery that form an interface between the CLB array
and the IOBs. This additional routing, called the
VersaRing, facilitates pin-swapping and pin-locking, such
that logic redesigns can adapt to existing PCB layouts.
Time-to-market is reduced, since PCBs and other system
components can be manufactured while the logic design is
still in progress.
Figure 6: Dual-Port Block SelectRAM
Table 5: Block SelectRAM Port Aspect Ratios
Width
Depth
ADDR Bus
Data Bus
1
4096
ADDR<11:0>
DATA<0>
2
2048
ADDR<10:0>
DATA<1:0>
4
1024
ADDR<9:0>
DATA<3:0>
8
512
ADDR<8:0>
DATA<7:0>
16
256
ADDR<7:0>
DATA<15:0>
WEB
ENB
RSTB
CLKB
ADDRB[#:0]
DIB[#:0]
WEA
ENA
RSTA
CLKA
ADDRA[#:0]
DIA[#:0]
DOA[#:0]
DOB[#:0]
RAMB4_S#_S#
ds022_06_121699
Figure 7: Virtex-E Local Routing
XCVE_ds_007
CLB
GRM
To
Adjacent
GRM
To Adjacent
GRM
Direct
Connection
To Adjacent
CLB
To Adjacent
GRM
To Adjacent
GRM
Direct Connection
To Adjacent
CLB
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XCV400E-6FG240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex⑩-E 1.8 V Field Programmable Gate Arrays |
| XCV400E-6FG240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex⑩-E 1.8 V Field Programmable Gate Arrays |
| XCV400E-6FG676C | 功能描述:IC FPGA 1.8V C-TEMP 676-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-E 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應商設備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XCV400E-6FG676I | 功能描述:IC FPGA 1.8V I-TEMP 676-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-E 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應商設備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XCV400E-6HQ240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex⑩-E 1.8 V Field Programmable Gate Arrays |
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