參數(shù)資料
型號: XCV405E-6BG560I
廠商: Xilinx Inc
文件頁數(shù): 15/118頁
文件大小: 0K
描述: IC FPGA 1.8V 560-MBGA
產(chǎn)品變化通告: FPGA Family Discontinuation 18/Apr/2011
標準包裝: 1
系列: Virtex®-E EM
LAB/CLB數(shù): 2400
邏輯元件/單元數(shù): 10800
RAM 位總計: 573440
輸入/輸出數(shù): 404
門數(shù): 129600
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 560-LBGA,金屬
供應商設備封裝: 560-MBGA(42.5x42.5)
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-4 (v3.0) March 21, 2014
Module 4 of 4
35
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
NA
VCCINT
V16
NA
VCCINT
V17
NA
VCCINT
V18
NA
VCCINT
W11
NA
VCCINT
W12
NA
VCCINT
W19
NA
VCCINT
W20
NA
VCCINT
Y11
NA
VCCINT
Y12
NA
VCCINT
Y19
NA
VCCINT
Y20
NA
VCCO_0
B6
NA
VCCO_0
M15
NA
VCCO_0
M14
NA
VCCO_0
L15
NA
VCCO_0
L14
NA
VCCO_0
H14
NA
VCCO_0
M13
NA
VCCO_0
C12
NA
VCCO_1
B25
NA
VCCO_1
C19
NA
VCCO_1
M18
NA
VCCO_1
M17
NA
VCCO_1
L17
NA
VCCO_1
H17
NA
VCCO_1
L16
NA
VCCO_1
M16
NA
VCCO_2
F29
NA
VCCO_2
M28
NA
VCCO_2
P23
NA
VCCO_2
R20
NA
VCCO_2
P20
NA
VCCO_2
R19
Table 5:
FG900 Fine-Pitch BGA Package — XCV812E
Bank
Description
Pin
NA
VCCO_2
N19
NA
VCCO_2
P19
NA
VCCO_3
AE29
NA
VCCO_3
W28
NA
VCCO_3
U23
NA
VCCO_3
U20
NA
VCCO_3
T20
NA
VCCO_3
V19
NA
VCCO_3
T19
NA
VCCO_3
U19
NA
VCCO_4
AJ25
NA
VCCO_4
AH19
NA
VCCO_4
W18
NA
VCCO_4
AC17
NA
VCCO_4
Y17
NA
VCCO_4
W17
NA
VCCO_4
W16
NA
VCCO_4
Y16
NA
VCCO_5
AJ6
NA
VCCO_5
Y15
NA
VCCO_5
W15
NA
VCCO_5
AC14
NA
VCCO_5
Y14
NA
VCCO_5
W14
NA
VCCO_5
W13
NA
VCCO_5
AH12
NA
VCCO_6
AE2
NA
VCCO_6
V12
NA
VCCO_6
U12
NA
VCCO_6
T12
NA
VCCO_6
U11
NA
VCCO_6
T11
NA
VCCO_6
U8
NA
VCCO_6
W3
Table 5:
FG900 Fine-Pitch BGA Package — XCV812E
Bank
Description
Pin
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