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參數(shù)資料
| 型號(hào)： | XCV405E-6BG560I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 57/118頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA 1.8V 560-MBGA |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Virtex®-E EM |
| LAB/CLB數(shù)： | 2400 |
| 邏輯元件/單元數(shù)： | 10800 |
| RAM 位總計(jì)： | 573440 |
| 輸入/輸出數(shù)： | 404 |
| 門數(shù)： | 129600 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 560-LBGA，金屬 |
| 供應(yīng)商設(shè)備封裝： | 560-MBGA（42.5x42.5） |
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Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-2 (v3.0) March 21, 2014
Module 2 of 4
39
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Input termination techniques include the following:
None
Parallel (Shunt)
These termination techniques can be applied in any combi-
nation. A generic example of each combination of termina-
tion methods appears in Figure 43.
Simultaneous Switching Guidelines
Ground bounce can occur with high-speed digital ICs when
multiple outputs change states simultaneously, causing
undesired transient behavior on an output, or in the internal
logic. This problem is also referred to as the Simultaneous
Switching Output (SSO) problem.
Ground bounce is primarily due to current changes in the
combined inductance of ground pins, bond wires, and
ground metallization. The IC internal ground level deviates
from the external system ground level for a short duration (a
few nanoseconds) after multiple outputs change state
simultaneously.
Ground bounce affects stable Low outputs and all inputs
because they interpret the incoming signal by comparing it
to the internal ground. If the ground bounce amplitude
exceeds the actual instantaneous noise margin, then a
non-changing input can be interpreted as a short pulse with
a polarity opposite to the ground bounce.
Table 21 provides the guidelines for the maximum number
of simultaneously switching outputs allowed per output
power/ground pair to avoid the effects of ground bounce.
Refer to Table 22 for the number of effective output
power/ground pairs for each Virtex-E device and package
combination.
Figure 43: Overview of Standard Input and Output
Termination Methods
x133_07_111699
Unterminated
Double Parallel Terminated
Series-Parallel Terminated Output
Driving a Parallel Terminated Input
V
TT
V
TT
V
REF
Series Terminated Output Driving
a Parallel Terminated Input
V
TT
V
REF
Unterminated Output Driving
a Parallel Terminated Input
V
TT
V
REF
V
TT
V
TT
V
REF
Series Terminated Output
V
REF
Z=50
Table 21:
Guidelines for Maximum Number of
Simultaneously Switching Outputs per
Power/Ground Pair
Standard
Package
BGA, FGA
LVTTL Slow Slew Rate, 2 mA drive
68
LVTTL Slow Slew Rate, 4 mA drive
41
LVTTL Slow Slew Rate, 6 mA drive
29
LVTTL Slow Slew Rate, 8 mA drive
22
LVTTL Slow Slew Rate, 12 mA drive
17
LVTTL Slow Slew Rate, 16 mA drive
14
LVTTL Slow Slew Rate, 24 mA drive
9
LVTTL Fast Slew Rate, 2 mA drive
40
LVTTL Fast Slew Rate, 4 mA drive
24
LVTTL Fast Slew Rate, 6 mA drive
17
LVTTL Fast Slew Rate, 8 mA drive
13
LVTTL Fast Slew Rate, 12 mA drive
10
LVTTL Fast Slew Rate, 16 mA drive
8
LVTTL Fast Slew Rate, 24 mA drive
5
LVCMOS
10
PCI
8
GTL
4
GTL+
4
HSTL Class I
18
HSTL Class III
9
HSTL Class IV
5
SSTL2 Class I
15
SSTL2 Class II
10
SSTL3 Class I
11
SSTL3 Class II
7
CTT
14
AGP
9
Note: This analysis assumes a 35 pF load for each output.
Table 22:
Virtex-E Extended Memory Family
Equivalent Power/Ground Pairs
Pkg/Part
XCV405E
XCV812E
BG560
56
FG676
56
FG900
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| XCV405E-6BG676C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
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| XCV405E-6BG900C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-6BG900I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-6FG404C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
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