參數(shù)資料
型號(hào)： XE8805AMI028LF
廠商： Semtech
文件頁數(shù)： 141/156頁
文件大?。?/td> 0K
描述： IC DAS 16BIT FLASH 8K MTP 64LQFP
標(biāo)準(zhǔn)包裝： 160
系列： XE880x
應(yīng)用： 感測機(jī)
核心處理器： Coolrisc816?
程序存儲(chǔ)器類型： 閃存（22 kB）
控制器系列： XE8000
RAM 容量： 512 x 8
接口： UART，USRT
輸入/輸出數(shù)： 24
電源電壓： 2.4 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
包裝： 托盤
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
產(chǎn)品目錄頁面： 585 (CN2011-ZH PDF)
配用： XE8000MP-ND - PROG BOARD AND PROSTART2 CARD
Semtech 2006
www.semtech.com
15-5
XE8805/05A
Condition 2 is satisfied when S0=1 at the rising edge of S1. The bit UsrtCond2 in RegUsrtCond2 is set when the
condition 2 is detected and the USRT interface is enabled. Condition 2 is asserted for both modes (receiver and
transmitter). The UsrtCond2 bit is read only and is cleared by all reset conditions and by writing any data to its
address.
Condition 2 occurrence also generates an interrupt on Irq_cond2.
15.7 Interrupts or polling
In receive mode, there are two possibilities for detecting condition 1 or 2: the detection of the condition can
generate an interrupt or the registers can be polled (reading and checking the RegUsrtCond1 and RegUsrtCond2
registers for the status of USRT communication).
15.8 Function description
The bit UsrtEnable in RegUsrtCtrl is used to enable the USRT interface and controls the PB[4] and PB[5] pins.
This bit puts these two port B lines in the open drain configuration requested to use the USRT interface.
If no external pull-ups are added on PB[4] and PB[5], the user can activate internal pull-ups by setting PBPullup[4]
and PBPullup[5] in RegPBPullup.
The bits UsrtEnWaitS0, UsrtEnWaitCond1, UsrtWaitS0 in RegUsrtCtrl are used for transmitter/receiver control
of USRT interface.
Figure 15-3 shows the unconditional clock stretching function which is enabled by setting UsrtEnWaitS0.
S0
UsrtWaitS0
write Reg UsrtBufferS1
Figure 15-3: S0 Stretching (UsrtEnWaitS0=1)
When UsrtEnWaitS0 is 1, the S0 line will be maintained at 0 after its falling edge (clock stretching). UsrtWaitS0 is
then set to 1, indicating that the S0 line is forced low. One can release S0 by writing to the RegUsrtBufferS1
register.
The same can be done in combination with condition 1 detection by setting the UsrtEnWaitCond1 bit. Figure 15-4
shows the conditional clock stretching function which is enabled by setting UsrtEnWaitCond1.
Not
Recommended
for
New
Designs
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XE8806AMI026LF 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Ultra Low-Power Low-Voltage
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