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Motorola, Inc. 2002.
MPC7450/MPC7451fact/rev.2
associative. L2 cache access is fully pipelined. The
MPC7450/MPC7451 also supports an L3 cache interface
with on-chip tags to support up to 2 MB of off-chip cache.
The L3 data bus is 64 bits wide, provides multiple SRAM
options, and affords critical quad-word forwarding to
reduce latency. The off-chip L3 storage can also be
configured as a local addressable memory. Finally, in
addition to supporting hardware table searching on a TLB
mss, the MPC7450/MPC7451 can be configured for
software table searching. In this case, TLB entries are
loaded by the systemsoftware.
The MPC7450/MPC7451 mcroprocessor contains
separate memory management units for instructions and
data, supporting 4 petabytes (252) of virtual memory and
up to 64 GB (236) of physical memory. The
MPC7450/MPC7451 also has four instruction block
address translation and four data block address
translation registers.
MPX BUS INTERFACE
MPC7450/MPC7451 mcroprocessors support the MPX
bus protocol with a 64-bit data bus and a 32- or 36-bit
address bus. Support is included for burst, split, pipelined,
and out-of-order transactions, in addition to data
streamng and data intervention (in SMP systems). The
interface provides snooping for data cache coherency. The
MPC7450/MPC7451 implements the cache coherency
protocol for multiprocessing support in hardware,
allowing access to systemmemory for additional caching
bus masters, such as DMA devices.
POWER MANAGEMENT
MPC7450/MPC7451 mcroprocessors feature a low-power
1.8V design with three power-saving user-programmable
modes—nap, doze (with bus snoop), and sleep—which
progressively reduce the power drawn by the processor
ALTIVEC TECHNOLOGY
AltiVec technology expands the capabilities of
Motorola’s fourth generation mcroprocessors by
providing leading-edge, general-purpose processing
performance while concurrently addressing high-
bandwidth data processing and algorithmc-intensive
computations in a single-chip solution.
ALTIVEC TECHNOLOGY:
Meets the computational demands of networking
infrastructure such as echo cancellation equipment and
basestation processing.
Enables faster more secure encryption methods optimzed
for the SIMD processing model.
CPU Speeds – Internal
Bus Frequency
Bus Protocol
Instructions per Clock
Integrated L2 Cache
Typical/Maximum
Power Dissipation
Die Size
Package
Process
Voltage
SPECint95 (estimated)
SPECfp95 (estimated)
Other Performance
Execution Units
Integrated L1 Cache
533, 667 and 733, and 867 MHz
64-bit
MPX/60x
4 (3 + Branch)
256 KB
32 KB instruction
32 KB data
14W /17W @ 533 MHz
106 mm
2
483 CBGA
0.18
μ
6LM CMOS
1.8V internal, 1.8/2.5V I/O
32.1 @ 733 MHz
23.9 @ 733 MHz
1324 Drystone 2.1 MIPS @ 733 MHz
Integer(4), Floating-Point, AltiVec(4),
Branch, Load/Store
133 MHz
MPC7450/MPC7451
Host Processors
Bus Interface
L3 Cache
1 or 2 MB
Provides compelling performance for multimedia-oriented desktop computers, desktop
publishing, and digital video processing.
Enables real-time processing of the most demanding data streams (MPEG-2 encode,
continuous speech recognition, real-time high-resolution 3-D memory for 3-D graphics.)
CONTACT INFORMATION
Motorola offers user’s manuals, application notes, sample code, and full local support for
all of its processors. For more information, visit: http://motorola.com/smartnetworks
For all other inquiries about Motorola products, please contact the Motorola Customer
Response Center at: 1-800-521-6274 or http://motorola.com/semconductors