參數(shù)資料
型號: XPC850SRZT50BU
英文描述: Microprocessor
中文描述: 微處理器
文件頁數(shù): 59/76頁
文件大小: 825K
代理商: XPC850SRZT50BU
MOTOROLA
MPC850 (Rev. A/B/C) Hardware Specifications
59
SMC Transparent AC Electrical Specifications
Figure 8-55. Ethernet Transmit Timing Diagram
8.8
SMC Transparent AC Electrical Specifications
Figure 8-21 provides the SMC transparent timings as shown in Figure 8-56.
Table 8-21. Serial Management Controller Timing
Num
Characteristic
All Frequencies
Unit
Min
Max
150
SMCLKx clock period
1
1
The ratio SyncCLK/SMCLKx must be greater or equal to 2/1.
100.00
ns
151
SMCLKx width low
50.00
ns
151a
SMCLKx width high
50.00
ns
152
SMCLKx rise/fall time
15.00
ns
153
SMTXDx active delay (from SMCLKx falling edge)
10.00
50.00
ns
154
SMRXDx/SMSYNx setup time
20.00
ns
155
SMRXDx/SMSYNx hold time
5.00
ns
TCLKx
128
TxDx
(Output)
128
TENA(RTSx)
(Input)
NOTES:
1.
2.
Transmit clock invert (TCI) bit in GSMR is set.
If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, then the
CSL bit is set in the buffer descriptor at the end of the frame transmission.
RENA(CDx)
(Input)
(NOTE 2)
133
134
132
131
130
129
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