
12
MPC850 (Rev. A/B/C) Hardware Specifications
MOTOROLA
Layout Practices
Part VI Bus Signal Timing
Table 6-6 provides the bus operation timing for the MPC850 at 50 MHz, 66 MHz, and 80
MHz. Timing information for other bus speeds can be interpolated by equation using the
MPC850 Electrical Specifications Spreadsheet found at http://www.mot.com/netcomm.
The maximum bus speed supported by the MPC850 is 50 MHz. Higher-speed parts must
be operated in half-speed bus mode (for example, an MPC850 used at 66 MHz must be
configured for a 33 MHz bus).
The timing for the MPC850 bus shown assumes a 50-pF load. This timing can be derated
by 1 ns per 10 pF. Derating calculations can also be performed using the MPC850 Electrical
Specifications Spreadsheet.
Table 6-6. Bus Operation Timing
1
Num
Characteristic
50 MHz
66 MHz
80 MHz
FFACT
Cap Load
(default
50 pF)
Unit
Min
Max
Min
Max
Min
Max
B1
CLKOUT period
20
—
30.30
—
25
—
—
—
ns
B1a
EXTCLK to CLKOUT phase
skew (EXTCLK > 15 MHz and
MF <= 2)
-0.90
0.90
-0.90
0.90
-0.90
0.90
—
50.00
ns
B1b
EXTCLK to CLKOUT phase
skew (EXTCLK > 10 MHz and
MF < 10)
-2.30
2.30
-2.30
2.30
-2.30
2.30
—
50.00
ns
B1c
CLKOUT phase jitter (EXTCLK
> 15 MHz and MF <= 2)
2
-0.60
0.60
-0.60
0.60
-0.60
0.60
—
50.00
ns
B1d
CLKOUT phase jitter
2
-2.00
2.00
-2.00
2.00
-2.00
2.00
—
50.00
ns
B1e
CLKOUT frequency jitter (MF <
10)
2
—
0.50
—
0.50
—
0.50
—
50.00
%
B1f
CLKOUT frequency jitter (10 <
MF < 500)
2
—
2.00
—
2.00
—
2.00
—
50.00
%
B1g
CLKOUT frequency jitter (MF >
500)
2
—
3.00
—
3.00
—
3.00
—
50.00
%
B1h
Frequency jitter on EXTCLK
3
—
0.50
—
0.50
—
0.50
—
50.00
%
B2
CLKOUT pulse width low
8.00
—
12.12
—
10.00
—
—
50.00
ns
B3
CLKOUT width high
8.00
—
12.12
—
10.00
—
—
50.00
ns
B4
CLKOUT rise time
—
4.00
—
4.00
—
4.00
—
50.00
ns
B5
CLKOUT fall time
—
4.00
—
4.00
—
4.00
—
50.00
ns
B7
CLKOUT to A[6–31],
RD/WR, BURST, D[0–31],
DP[0–3] invalid
5.00
—
7.58
—
6.25
—
0.250
50.00
ns
B7a
CLKOUT to TSIZ[0–1], REG,
RSV, AT[0–3], BDIP, PTR invalid
5.00
—
7.58
—
6.25
—
0.250
50.00
ns