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| 型號(hào)： | XQ4005E-4CB164M |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | 現(xiàn)場(chǎng)可編程門(mén)陣列（FPGA） |
| 文件頁(yè)數(shù)： | 7/36頁(yè) |
| 文件大?。?/td> | 304K |
| 代理商： | XQ4005E-4CB164M |
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QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000
Product Specification
1-800-255-7778XQ4000E CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature). Values apply to all
XQ4000E devices unless otherwise noted.
Symbol
Description
-3
-4
Units
Min
Max
Min
Max
Combinatorial Delays
T
ILO
T
IHO
T
HH0O
T
HH1O
T
HH2O
CLB Fast Carry Logic
F/G inputs to X/Y outputs
-
2.01
-
2.7
ns
F/G inputs via H to X/Y outputs
-
4.3
-
4.7
ns
C inputs via SR through H to X/Y outputs
-
3.3
-
4.1
ns
C inputs via H to X/Y outputs
-
3.6
-
3.7
ns
C inputs via D
IN
through H to X/Y outputs
-
3.6
-
4.5
ns
T
OPCY
T
ASCY
T
INCY
T
SUM
T
BYP
Sequential Delays
Operand inputs (F1, F2, G1, G4) to C
OUT
Add/Subtract input (F3) to C
OUT
Initialization inputs (F1, F3) to C
OUT
C
IN
through function generators to X/Y outputs
C
IN
to C
OUT
, bypass function generators
-
2.6
-
3.2
ns
-
4.4
-
5.5
ns
-
1.7
-
1.7
ns
-
3.3
-
3.8
ns
-
0.7
-
1.0
ns
T
CKO
Clock K to outputs Q
-
2.8
-
3.7
ns
Setup Time before Clock K
T
ICK
T
IHCK
T
HH0CK
T
HH1CK
T
HH2CK
T
DICK
T
ECCK
T
RCK
T
CCK
T
CHCK
F/G inputs
3.0
-
4.0
-
ns
F/G inputs via H
4.6
-
6.1
-
ns
C inputs via H0 through H
3.6
-
4.5
-
ns
C inputs via H1 through H
4.1
-
5.0
-
ns
C inputs via H2 through H
3.8
-
4.8
-
ns
C inputs via D
IN
C inputs via EC
2.4
-
3.0
-
ns
3.0
-
4.0
-
ns
C inputs via S/R, going Low (inactive)
4.0
-
4.2
-
ns
C
IN
input via F/G
C
IN
input via F/G and H
2.1
-
2.5
-
ns
3.5
-
4.2
-
ns
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