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參數資料
| 型號： | XQ4013E |
| 廠商： | Xilinx, Inc. |
| 元件分類： | FPGA |
| 英文描述： | QPRO XQ4000E/EX QML High-Reliability FPGAs |
| 中文描述： | QPRO XQ4000E/EX QML第高可靠性的FPGA |
| 文件頁數： | 16/36頁 |
| 文件大小： | 304K |
| 代理商： | XQ4013E |
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R
XQ4000E IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature). For Propagation
Delays, slew-rate = fast unless otherwise noted. Values
apply to all XQ4000E devices unless otherwise noted.
Symbol
Propagation Delays (TTL Output Levels)
T
OKPOF
Clock (OK) to pad, fast
T
OKPOS
Clock (OK) to pad, slew-rate limited
T
OPF
Output (O) to pad, fast
T
OPS
Output (O) to pad, slew-rate limited
T
TSHZ
3-state to pad High-Z, slew-rate independent
T
TSONF
3-state to pad active and valid, fast
T
TSONS
3-state to pad active and valid, slew-rate limited
Propagation Delays (CMOS Output Levels)
T
OKPOFC
Clock (OK) to pad, fast
T
OKPOSC
Clock (OK) to pad, slew-rate limited
T
OPFC
Output (O) to pad, fast
T
OPSC
Output (O) to pad, slew-rate limited
T
TSHZC
3-state to pad High-Z, slew-rate independent
T
TSONFC
3-state to pad active and valid, fast
T
TSONSC
3-state to pad active and valid, slew-rate limited
Setup and Hold Times
T
OOK
Output (O) to clock (OK) setup time
T
OKO
Output (O) to clock (OK) hold time
T
ECOK
Clock enable (EC) to clock (OK) setup
T
OKEC
Clock enable (EC) to clock (OK) hold
Clock
T
CH
Clock High
T
CL
Clock Low
Global Set/Reset
(3)
T
RRO
Delay from GSR net to pad
T
MRW
GSR width
T
MRO
GSR inactive to first active clock (OK) edge
Notes:
1.
Output timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Slew-rate limited output rise/fall
times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see the
“
Additional XC4000 Data
”
section on the Xilinx web site,
www.xilinx.com/partinfo/databook.htm
.
2.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
3.
Timing is based on the XC4005E. For other devices see the XACT timing calculator.
Description
-3
-4
Units
Min
Max
Min
Max
-
-
-
-
-
-
-
6.5
9.5
5.5
8.6
4.2
8.1
11.1
-
-
-
-
-
-
-
7.5
11.5
8.0
12.0
10.0
10.0
13.7
ns
ns
ns
ns
ns
ns
ns
-
-
-
-
-
-
-
7.8
11.6
9.7
13.4
4.3
7.6
11.4
-
-
-
-
-
-
-
9.5
13.5
10.0
14.0
5.2
9.1
13.1
ns
ns
ns
ns
ns
ns
ns
4.6
0
3.5
1.2
-
-
-
-
5.0
0
4.8
1.2
-
-
-
-
ns
ns
ns
ns
4.0
4.0
-
-
4.5
4.5
-
-
ns
ns
-
11.8
-
-
-
15.0
-
-
ns
ns
ns
11.5
11.5
13.0
13.0
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相關代理商/技術參數 |
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| XQ4013E-3BG191M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPRO XQ4000E/EX QML High-Reliability FPGAs |
| XQ4013E-3BG191N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPRO XQ4000E/EX QML High-Reliability FPGAs |
| XQ4013E-3BG196M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4013E-3BG196N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4013E-3CB191M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
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