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參數(shù)資料
| 型號(hào)： | XQR1701LSERIES |
| 英文描述： | QPro Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR) |
| 中文描述： | QPro系列配置PROM的（學(xué)琴），包括抗輻射系列（XQR） |
| 文件頁(yè)數(shù)： | 8/17頁(yè) |
| 文件大?。?/td> | 171K |
| 代理商： | XQR1701LSERIES |
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R
Connecting Configuration PROMs
Connecting the FPGA device with the configuration PROM
(see
Figure 6
).
The DATA output(s) of the PROM(s) drives the D
IN
input of the lead FPGA device.
The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s) (in Master Serial mode only).
The CEO output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
The OE/RESET input of all PROMs is best driven by
the INIT output of the lead FPGA device. This
connection assures that the PROM address counter is
reset before the start of any (re)configuration, even
when a reconfiguration is initiated by a V
CC
glitch.
The PROM CE input can be driven from the DONE pin.
The CE input of the first (or only) PROM can be driven
by the DONE output of the first FPGA device, provided
that DONE is not permanently grounded. CE can also
be permanently tied Low, but this keeps the DATA
output active and causes an unnecessary supply
current of 20 mA maximum.
Express/SelectMap mode is similar to slave serial
mode. The DATA is clocked out of the PROM one byte
per CCLK instead of one bit per CCLK cycle. See
FPGA
data
sheets
requirements.
for
special
configuration
Initiating FPGA Configuration
The XQ(R)18V04 devices incorporate a pin named CF that
is controllable through the JTAG CONFIG instruction. Exe-
cuting the CONFIG instruction through JTAG pulses the CF
low for 300-500 ns, which resets the FPGA and initiates
configuration.
The CF pin must be connected to the PROGRAM pin on the
FPGA(s) to use this feature.
The JTAG Programmer software can also issue a JTAG
CONFIG command to initiate FPGA configuration through
the "Load FPGA" setting.
Selecting Configuration Modes
The XQ(R)18V04 accommodates serial and parallel meth-
ods of configuration. The configuration modes are select-
able through a user control register in the XQ(R)18V04
device. This control register is accessible through JTAG,
and is set using the "Parallel mode" setting on the Xilinx
JTAG Programmer software. Serial output is the default pro-
gramming mode.
Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block
(CLB) and their associated interconnections are established
by a configuration program. The program is loaded either
automatically upon power up, or on command, depending
on the state of the three FPGA mode pins. In Master Serial
mode, the FPGA automatically loads the configuration pro-
gram from an external memory. Xilinx PROMs are designed
to accommodate the Master Serial mode.
Upon power-up or reconfiguration, an FPGA enters the
Master Serial mode whenever all three of the FPGA
mode-select pins are Low (M0=0, M1=0, M2=0). Data is
read from the PROM sequentially on a single data line. Syn-
chronization is provided by the rising edge of the temporary
signal CCLK, which is generated by the FPGA during con-
figuration.
Master Serial Mode provides a simple configuration inter-
face. Only a serial data line, a clock line, and two control
lines are required to configure an FPGA. Data from the
PROM is read sequentially, accessed via the internal
address and bit counters which are incremented on every
valid rising edge of CCLK. If the user-programmable,
dual-function D
IN
pin on the FPGA is used only for configu-
ration, it must still be held at a defined level during normal
operation. The Xilinx FPGA families take care of this auto-
matically with an on-chip pull-up resistor.
Cascading Configuration PROMs
For multiple FPGAs configured as a serial daisy-chain, or a
single FPGA requiring larger configuration memories in a
serial or SelectMAP configuration mode, cascaded PROMs
provide additional memory (
Figure 5
). Multiple XQ(R)18V04
devices can be concatenated by using the CEO output to
drive the CE input of the downstream device. The clock
inputs and the data outputs of all XQ(R)18V04 devices in
the chain are interconnected. After the last bit from the first
PROM is read, the next clock signal to the PROM asserts its
CEO output Low and drives its DATA line to a high-imped-
ance state. The second PROM recognizes the Low level on
its CE input and enables its DATA output. See
Figure 6
.
After configuration is complete, the address counters of all
cascaded PROMs are reset if the PROM OE/RESET pin
goes Low.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XQ1701L-CC44B | Configuration EPROM |
| XQ1701L-CC44M | Configuration EPROM |
| XQ1701LSERIES | QPro Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR) |
| XQ1701L-SO20N | Configuration EPROM |
| XQR4000XL | QPRO XQR4000XL Radiation Hardened FPGAs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XQR1701LSO20M | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:QPro Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR) |
| XQR1701LSO20N | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:QPro Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR) |
| XQR1701LSO20V | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:QPro Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR) |
| XQR18V04 | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs |
| XQS14+A2FZ | 制造商:Panasonic Industrial Company 功能描述:SCREW (1/10) |
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