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參數(shù)資料
| 型號(hào)： | XQR4000XL |
| 英文描述： | QPRO XQR4000XL Radiation Hardened FPGAs |
| 中文描述： | QPRO XQR4000XL抗輻射FPGA的 |
| 文件頁(yè)數(shù)： | 14/20頁(yè) |
| 文件大?。?/td> | 201K |
| 代理商： | XQR4000XL |
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Global Early Clock BUFEs 1, 2, 5, and 6 Setup and Hold for IFF and FCL
(1,2)
Global Early Clock BUFEs 3, 4, 7, and 8 Setup and Hold for IFF and FCL
(1,2)
Symbol
Description
Device
-3
Min
No Delay
T
PSEN
/T
PHEN
T
PFSEN
/T
PFHEN
Global early clock and IFF
(3)
Global early clock and FCL
(4)
XQR4013XL
XQR4036XL
XQR4062XL
1.2 / 4.7
1.2 / 6.7
1.2 / 8.4
Partial Delay
T
PSEPN
/T
PHEP
T
PFSEP
/T
PFHEP
Global early clock and IFF
(3)
Global early clock and FCL
(4)
XQR4013XL
XQR4036XL
XQR4062XL
6.4 / 0.0
7.0 / 0.8
9.0 / 0.8
Full Delay
T
PSEPD
/T
PHED
Global early clock and IFF
(3)
XQR4013XL
XQR4036XL
XQR4062XL
12.0 / 0.0
13.8 / 0.0
13.1 / 0.0
Notes:
1.
2.
The XQR4013XL, XQR4036XL, and XQR4062XL have significantly faster partial and full delay setup times than other devices.
Input setup time is measured with the fastest route and the lightest load. Input hold time is measured using the furthest distance and
a reference load of one clock pin per IOB as well as driving all accessible CLB flip-flops. For designs with a smaller number of clock
loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin
no-delay input hold specification.
IFF = Input Flip-Flop or Latch
FCL = Fast Capture Latch
3.
4.
Symbol
Description
Device
-3
Min
No Delay
T
PSEN
/T
PHEN
T
PFSEN
/T
PFHEN
Global early clock and IFF
(3)
Global early clock and FCL
(4)
XQR4013XL
XQR4036XL
XQR4062XL
1.2 / 4.7
1.2 / 6.7
1.2 / 8.4
Partial Delay
T
PSEPN
/T
PHEP
T
PFSEP
/T
PFHEP
Global early clock and IFF
(3)
Global early clock and FCL
(4)
XQR4013XL
XQR4036XL
XQR4062XL
5.4 / 0.0
6.4 / 0.8
8.4 / 1.5
Full Delay
T
PSEPD
/T
PHED
Global early clock and IFF
(3)
XQR4013XL
XQR4036XL
XQR4062XL
10.0 / 0.0
12.2 / 0.0
13.1 / 0.0
Notes:
1.
2.
The XQR4013XL, XQR4036XL, and XQR4062XL have significantly faster partial and full delay setup times than other devices.
Input setup time is measured with the fastest route and the lightest load. Input hold time is measured using the furthest distance and
a reference load of one clock pin per IOB as well as driving all accessible CLB flip-flops. For designs with a smaller number of clock
loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin
no-delay input hold specification.
IFF = Input Flip-Flop or Latch
FCL = Fast Capture Latch
3.
4.
This Material Copyrighted by Its Respective Manufacturer
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