參數(shù)資料
型號(hào)： XR16C2850
廠商： Exar Corporation
英文描述： 3.3V AND 5V DUART WITH 128-BYTE FIFO
中文描述： 3.3V和5V杜阿爾特128字節(jié)FIFO
文件頁(yè)數(shù)： 21/43頁(yè)
文件大?。?/td> 611K
代理商： XR16C2850
XR16C2850
REV. 2.0.0
3.3V AND 5V DUART WITH 128-BYTE FIFO
á
21
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when
RHR has a data character in the non-FIFO mode
or
when the receive FIFO has reached the programmed
trigger level in the FIFO mode.
Logic 0 = Disable the receive data ready interrupt
(default).
Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This bit enables the Transmit Ready interrupt which is
issued whenever the THR becomes empty in the non-
FIFO mode or when data in the FIFO falls below the
programmed trigger level in the FIFO mode. If the
THR is empty when this bit is enabled, an interrupt
will be generated.
Logic 0 = Disable Transmit Ready interrupt
(default).
Logic 1 = Enable Transmit Ready interrupt.
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3 or 4 is a logic 1,
it will generate an interrupt to inform the host control-
ler about the error status of the current data byte in
FIFO. LSR bits 1-4 generate an interrupt immediately
when the character has been received.
Logic 0 = Disable the receiver line status interrupt
(default).
Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
Logic 0 = Disable the modem status register inter-
rupt (default).
Logic 1 = Enable the modem status register inter-
rupt.
IER[4]: Sleep Mode Enable (requires EFR bit-4 =
1)
Logic 0 = Disable Sleep Mode (default).
Logic 1 = Enable Sleep Mode. See Sleep Mode
section for further details.
IER[5]: Xoff Interrupt Enable (requires EFR bit-
4=1)
Logic 0 = Disable the software flow control, receive
Xoff interrupt. (default)
Logic 1 = Enable the software flow control, receive
Xoff interrupt. See Software Flow Control section
for details.
IER[6]: RTS# Output Interrupt Enable (requires
EFR bit-4=1)
Logic 0 = Disable the RTS# interrupt (default).
Logic 1 = Enable the RTS# interrupt. The UART
issues an interrupt when the RTS# pin makes a
transition from low to high.
IER[7]: CTS# Input Interrupt Enable (requires EFR
bit-4=1)
Logic 0 = Disable the CTS# interrupt (default).
Logic 1 = Enable the CTS# interrupt. The UART
issues an interrupt when CTS# pin makes a transi-
tion from low to high.
4.4
I
NTERRUPT
S
TATUS
R
EGISTER
(ISR) - R
EAD
-
O
NLY
The UART provides multiple levels of prioritized inter-
rupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with
six interrupt status bits. Performing a read cycle on
the ISR will give the user the current highest pending
interrupt level to be serviced, others are queued up to
be serviced next. No other interrupts are acknowl-
edged until the pending interrupt is serviced. The In-
terrupt Source Table, Table 9, shows the data values
(bit 0-5) for the interrupt priority levels and the inter-
rupt sources associated with each of these interrupt
levels.
4.4.1
Interrupt Generation:
LSR is by any of the LSR bits 1, 2, 3 and 4.
RXRDY is by RX trigger level.
RXRDY Time-out is by a 4-char plus 12 bits delay
timer.
TXRDY is by TX trigger level or TX FIFO empty (or
transmitter empty in auto RS-485 control).
MSR is by any of the MSR bits 0, 1, 2 and 3.
Receive Xoff/Special character is by detection of a
Xoff or Special character.
CTS# is when its transmitter toggles the input pin
(from low to high) during auto CTS flow control
enabled by EFR bit-7.
RTS# is when its receiver toggles the output pin
(from low to high) during auto RTS flow control
enabled by EFR bit-6.
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