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參數(shù)資料
| 型號： | XR16C2850 |
| 廠商： | Exar Corporation |
| 英文描述： | 3.3V AND 5V DUART WITH 128-BYTE FIFO |
| 中文描述： | 3.3V和5V杜阿爾特128字節(jié)FIFO |
| 文件頁數(shù)： | 29/43頁 |
| 文件大?。?/td> | 611K |
| 代理商： | XR16C2850 |
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XR16C2850
REV. 2.0.0
3.3V AND 5V DUART WITH 128-BYTE FIFO
á
29
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables IER
bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7
to be modified. After modifying any enhanced bits,
EFR bit-4 can be set to a logic 0 to latch the new val-
ues. This feature prevents legacy software from alter-
ing or overwriting the enhanced functions once set.
Normally, it is recommended to leave it enabled, logic
1.
Logic 0 = modification disable/latch enhanced fea-
tures. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and
MCR bits 5-7 are saved to retain the user settings.
After a reset, the IER bits 4-7, ISR bits 4-5, FCR
bits 4-5, and MCR bits 5-7are set to a logic 0 to be
compatible with ST16C550 mode (default).
Logic 1 = Enables the above-mentioned register
bits to be modified by the user.
EFR[5]: Special Character Detect Enable
Logic 0 = Special Character Detect Disabled
(default).
Logic 1 = Special Character Detect Enabled. The
UART compares each incoming receive character
with data in Xoff-2 register. If a match exists, the
receive data will be transferred to FIFO and ISR bit-
4 will be set to indicate detection of the special
character. Bit-0 corresponds with the LSB bit of the
receive character. If flow control is set for compar-
ing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control
and special character work normally. However, if
flow control is set for comparing Xon2, Xoff2
(EFR[1:0]= ‘01’) then flow control works normally,
but Xoff2 will not go to the FIFO, and will generate
an Xoff interrupt and a special character interrupt, if
enabled via IER bit-5.
EFR[6]: Auto RTS Flow Control Enable
RTS# output may be used for hardware flow control
by setting EFR bit-6 to logic 1. When Auto RTS is se-
lected, an interrupt will be generated when the re-
ceive FIFO is filled to the programmed trigger level
and RTS de-asserts to a logic 1 at the next upper trig-
ger level or hysteresis level. RTS# will return to a logic
0 when FIFO data falls below the next lower trigger
level. The RTS# output must be asserted (logic 0) be-
fore the auto RTS can take effect. RTS# pin will func-
tion as a general purpose output when hardware flow
control is disabled.
Logic 0 = Automatic RTS flow control is disabled
(default).
Logic 1 = Enable Automatic RTS flow control.
T
ABLE
15: S
OFTWARE
F
LOW
C
ONTROL
F
UNCTIONS
EFR
BIT
-3
C
ONT
-3
EFR
BIT
-2
C
ONT
-2
EFR
BIT
-1
C
ONT
-1
EFR
BIT
-0
C
ONT
-0
T
RANSMIT
AND
R
ECEIVE
S
OFTWARE
F
LOW
C
ONTROL
0
0
0
0
No TX and RX flow control (default and reset)
0
0
X
X
No transmit flow control
1
0
X
X
Transmit Xon1, Xoff1
0
1
X
X
Transmit Xon2, Xoff2
1
1
X
X
Transmit Xon1 and Xon2, Xoff1 and Xoff2
X
X
0
0
No receive flow control
X
X
1
0
Receiver compares Xon1, Xoff1
X
X
0
1
Receiver compares Xon2, Xoff2
1
0
1
1
Transmit Xon1, Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0
1
1
1
Transmit Xon2, Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1
1
1
1
Transmit Xon1 and Xon2, Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
0
0
1
1
No transmit flow control,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
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| XR16C2850_05 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS |
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| XR16C2850CJ-0A-EB | 功能描述:UART 接口集成電路 Supports C2850 44 ld PLCC, ISA Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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| XR16C2850CJ-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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