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參數(shù)資料
| 型號： | XR16C2850CM48 |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3.3V AND 5V DUART WITH 128-BYTE FIFO |
| 中文描述： | 2 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 1 MM HEIGHT, TQFP-48 |
| 文件頁數(shù)： | 27/43頁 |
| 文件大?。?/td> | 611K |
| 代理商： | XR16C2850CM48 |
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XR16C2850
REV. 2.0.0
3.3V AND 5V DUART WITH 128-BYTE FIFO
á
27
4.11 E
NHANCED
M
ODE
S
ELECT
R
EGISTER
(EMSR)
This register replaces SPR (during a Write) and is ac-
cessible only when FCTR[6] = 1.
EMSR[1:0]: Receive/Transmit FIFO Count (Write-
Only)
When Scratchpad Swap (FCTR[6]) is asserted, EM-
SR bits 1-0 controls what mode the FIFO Level
Counter is operating in.
During Alternate RX/TX FIFO Counter Mode, the first
value read after EMSR bits 1-0 have been asserted
will always be the RX FIFO Counter. The second val-
ue read will correspond with the TX FIFO Counter.
The next value will be the RX FIFO Counter again,
then the TX FIFO Counter and so on and so forth.
EMSR[3:2]: Reserved
EMSR[5:4]: Extended RTS Hysteresis
EMSR[7:6]: Reserved
4.12 FIFO L
EVEL
R
EGISTER
(FLVL) - R
EAD
-O
NLY
The FIFO Level Register replaces the Scratchpad
Register (during a Read) when FCTR[6] = 1. Note
that this is not identical to the FIFO Data Count Reg-
ister which can be accessed when LCR = 0xBF.
FLVL[7:0]: FIFO Level Register
This register provides the FIFO counter level for the
RX FIFO or the TX FIFO or both depending on EM-
SR[1:0]. See Table 12 for details.
4.13 B
AUD
R
ATE
G
ENERATOR
R
EGISTERS
(DLL
AND
DLM) - R
EAD
/W
RITE
The concatenation of the contents of DLM and DLL
gives the 16-bit divisor value which is used to calcu-
late the baud rate:
Baud Rate = (Clock Frequency / 16) / Divisor
See MCR bit-7 and the baud rate table also.
4.14 D
EVICE
I
DENTIFICATION
R
EGISTER
(DVID) - R
EAD
O
NLY
This register contains the device ID (0x12 for
XR16C2850). Prior to reading this register, DLL and
DLM should be set to 0x00.
4.15 D
EVICE
R
EVISION
R
EGISTER
(DREV) - R
EAD
O
NLY
This register contains the device revision information.
For example, 0x01 means revision A. Prior to reading
this register, DLL and DLM should be set to 0x00.
4.16 T
RIGGER
L
EVEL
/ FIFO D
ATA
C
OUNT
R
EGISTER
(TRG) - W
RITE
-O
NLY
User Programmable Transmit/Receive Trigger Level
Register.
TRG[7:0]: Trigger Level Register
These bits are used to program desired trigger levels
when trigger Table-D is selected. FCTR bit-7 selects
between programming the RX Trigger Level (a logic
0) and the TX Trigger Level (a logic 1).
4.17 FIFO D
ATA
C
OUNT
R
EGISTER
(FC) - R
EAD
-O
NLY
This register is accessible when LCR = 0xBF. Note
that this register is not identical to the FIFO Level
Register which is located in the general register set
when FCTR bit-6 = 1.
FC[7:0]: FIFO Data Count Register
Transmit/Receive FIFO Count. Number of characters
in Transmit (FCTR[7] = 1) or Receive FIFO (FCTR[7]
= 0) can be read via this register.
T
ABLE
12: S
CRATCHPAD
S
WAP
S
ELECTION
FCTR[6]
EMSR[1]
EMSR[0]
Scratchpad is
0
X
X
Scratchpad
1
0
0
RX FIFO Counter Mode
1
0
1
TX FIFO Counter Mode
1
1
0
RX FIFO Counter Mode
1
1
1
Alternate RX/TX FIFO
Counter Mode
T
ABLE
13: A
UTO
RTS H
YSTERESIS
EMSR
B
IT
-5
EMSR
B
IT
-4
FCTR
B
IT
-1
FCTR
B
IT
-0
RTS#
H
YSTERESIS
(C
HARACTERS
)
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
±4
±6
±8
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
±8
±16
±24
±32
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
±40
±44
±48
±52
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
±12
±20
±28
±36
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XR16C2850CP40 | 3.3V AND 5V DUART WITH 128-BYTE FIFO |
| XR16C2850IJ44 | 3.3V AND 5V DUART WITH 128-BYTE FIFO |
| XR16C2850IM48 | 3.3V AND 5V DUART WITH 128-BYTE FIFO |
| XR16C2850IP40 | 3.3V AND 5V DUART WITH 128-BYTE FIFO |
| XR16C2850CJ | DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16C2850CM-F | 功能描述:UART 接口集成電路 2.97V-5.5V 128B FIFO temp 0C to 70C; UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C2850CMTR-F | 制造商:Exar Corporation 功能描述:UART 2-CH 128Byte FIFO 3.3V/5V 48-Pin TQFP T/R 制造商:Exar Corporation 功能描述:XR16C2850CMTR-F |
| XR16C2850CP | 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL |
| XR16C2850CP40 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V AND 5V DUART WITH 128-BYTE FIFO |
| XR16C2850IJ | 制造商:Exar Corporation 功能描述:UART 2-CH 128Byte FIFO 3.3V/5V 44-Pin PLCC 制造商:Rochester Electronics LLC 功能描述: |
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