參數(shù)資料
型號(hào): XR16C2852CJ-F
廠商: Exar Corporation
文件頁(yè)數(shù): 1/51頁(yè)
文件大?。?/td> 0K
描述: IC UART FIFO 128B 44PLCC
標(biāo)準(zhǔn)包裝: 27
特點(diǎn): *
通道數(shù): 2,DUART
FIFO's: 128 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.97 V ~ 5.5 V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類(lèi)型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線(xiàn))
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 管件
其它名稱(chēng): XR16C2852CJ-F-ND
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
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XR16C2852
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
FEBRUARY 2005
REV. 2.1.1
GENERAL DESCRIPTION
The XR16C28521 (2852) is a dual universal
asynchronous receiver and transmitter (UART). The
device operates at 2.97V to 5.5V and is pin-to-pin
compatible to Exar’s ST16C2552 and XR16L2752.
The 2852 register set is compatible to the
ST16C2552 and the XR16L2752 enhanced features.
It supports the Exar’s enhanced features of 128 bytes
of TX and RX FIFOs, programmable FIFO trigger
level and FIFO level counters, automatic hardware
(RTS/CTS) and software flow control, automatic RS-
485 half duplex direction control output and a
complete modem interface. Onboard registers
provide the user with operational status and data
error flags. An internal loopback capability allows
system diagnotics. Independent programmable baud
rate generators are provided in each channel to
select data rates up to 3.125 Mbps at 5V. The 2852 is
available in the 44-pin PLCC package.
NOTE: 1 Covered by U.S. Patent #5,649,122 and #5,949,787
APPLICATIONS
Portable Appliances
Telecommunication Network Routers
Ethernet Network Routers
Cellular Data Devices
Factory Automation and Process Controls
FEATURES
Added feature in devices with a top mark date code of
"F2 YYWW" and newer:
5V tolerant inputs
0 ns address hold time (TAH)
Pin-to-pin compatible to Exar’s ST16C2552 and
XR16L2752
Improved version of PC16C552
Two independent UART channels
Register set compatible to 16C550
Up to 3 Mbps at 5V, and 2 Mbps at 3.3V
Transmit and Receive FIFOs of 128 bytes
Programmable TX and RX FIFO Trigger Levels
Transmit and Receive FIFO Level Counters
Automatic Hardware (RTS/CTS) Flow Control
Selectable Auto RTS Flow Control Hysteresis
Automatic Software (Xon/Xoff) Flow Control
Automatic
RS-485
Half-duplex
Direction
Control Output
Wireless Infrared (IrDA 1.0) Encoder/Decoder
Automatic sleep mode
Alternate Function Register
Device Identification and Revision
Crystal oscillator or external clock input
2.97 to 5.5 volt operation
Industrial and commercial temperature ranges
FIGURE 1. XR16C2852 BLOCK DIAGRAM
MFA#
(OP2A#,
BAUDOUTA#, or
RXRDYA#)
MFB#
(OP2B#,
BAUDOUTB#, or
RXRDYB#)
XTAL1
XTAL2
Crystal Osc/Buffer
TXA (or TXIRA)
8-bit Data
Bus
Interface
UART Channel A
128 Byte TX FIFO
128 Byte RX FIFO
BRG
IR
ENDEC
TX & RX
UART
Regs
2.97V to 5.5V VCC
GND
UART Channel B
(same as Channel A)
A2:A0
D7:D0
CS#
CHSEL
INTA
INTB
IOW#
IOR#
Reset
TXRDYA#
TXRDYB#
CTS#A/B, RI#A/B,
CD#A/B, DSR#A/B
RXA (or RXIRA)
Modem Control Logic
DTR#A/B, RTS#A/B
TXB (or TXIRB)
RXB (or RXIRB)
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