XR16C2852
xr
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
REV. 2.1.1
44
FIGURE 20. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B
FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B
RX
RXRDY#
IOR#
INT
D0:D7
Start
Bit
D0:D7
Stop
Bit
D0:D7
T
SSR
1 Byte
in RHR
Active
Data
Ready
Active
Data
Ready
Active
Data
Ready
1 Byte
in RHR
1 Byte
in RHR
T
SSR
T
SSR
RXNFM
T
RR
T
RR
T
RR
T
SSR
T
SSR
T
SSR
(Reading data
out of RHR)
TX
TXRDY#
IOW#
INT*
D0:D7
Start
Bit
D0:D7
Stop
Bit
D0:D7
T
WT
TXNonFIFO
T
WT
T
WT
T
WRI
T
WRI
T
WRI
T
SRT
T
SRT
T
SRT
*INT is cleared when the ISR is read or when data is loaded into the THR.
ISR is read
(Loading data
into THR)
(Unloading)
IER[1]
enabled