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REV. 2.1.1 II 4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION............" />

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參數(shù)資料

型號：	XR16C2852IJTR-F
廠商：	Exar Corporation
文件頁數(shù)：	47/51頁
文件大?。?/td>	0K
描述：	IC UART FIFO 128B 44PLCC
標準包裝：	500
特點：	*
通道數(shù)：	2，DUART
FIFO's：	128 字節(jié)
規(guī)程：	RS232，RS485
電源電壓：	2.97 V ~ 5.5 V
帶自動流量控制功能：	是
帶IrDA 編碼器/解碼器：	是
帶故障啟動位檢測功能：	是
帶調制解調器控制功能：	是
帶CMOS：	是
安裝類型：	表面貼裝
封裝/外殼：	44-LCC（J 形引線）
供應商設備封裝：	44-PLCC（16.59x16.59）
包裝：	帶卷 (TR)

xr

XR16C2852

2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS

REV. 2.1.1

II

4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION................................................................ 24

4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 25

4.4.1 INTERRUPT GENERATION: ...................................................................................................................................... 25

4.4.2 INTERRUPT CLEARING: ........................................................................................................................................... 25

TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL ....................................................................................................................... 26

4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ..................................................................................... 26

TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION .......................................................................... 27

4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ..................................................................................... 28

TABLE 11: PARITY SELECTION ........................................................................................................................................................ 29

4.7 ALTERNATE FUNCTION REGISTER (AFR) - READ/WRITE ....................................................................... 29

4.8 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE 30

4.9 LINE STATUS REGISTER (LSR) - READ ONLY ........................................................................................... 31

4.10 MODEM STATUS REGISTER (MSR) - READ ONLY .................................................................................. 32

4.11 SCRATCH PAD REGISTER (SPR) - READ/WRITE .................................................................................... 33

4.12 ENHANCED MODE SELECT REGISTER (EMSR) ...................................................................................... 33

TABLE 12: SCRATCHPAD SWAP SELECTION .................................................................................................................................... 33

TABLE 13: EXTENDED RTS HYSTERESIS ........................................................................................................................................ 34

4.13 FIFO LEVEL REGISTER (FLVL) - READ-ONLY ......................................................................................... 34

4.14 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE .............................................. 34

4.15 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY .................................................................... 35

4.16 DEVICE REVISION REGISTER (DREV) - READ ONLY .............................................................................. 35

4.17 TRIGGER LEVEL / FIFO DATA COUNT REGISTER (TRG) - WRITE-ONLY ............................................. 35

4.18 FIFO DATA COUNT REGISTER (FC) - READ-ONLY ................................................................................. 35

4.19 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE ....................................................................... 35

TABLE 14: TRIGGER TABLE SELECT ............................................................................................................................................... 35

4.20 ENHANCED FEATURE REGISTER (EFR) .................................................................................................. 36

TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS........................................................................................................................ 36

4.21 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE ................ 37

TABLE 16: UART RESET CONDITIONS FOR CHANNEL A AND B............................................................................................ 38

ABSOLUTE MAXIMUM RATINGS .................................................................................. 39

TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) 39

ELECTRICAL CHARACTERISTICS................................................................................ 39

DC ELECTRICAL CHARACTERISTICS.............................................................................................................. 39

FIGURE 14. XR16C2852 VOL SINK CURRENT CHART ................................................................................................................... 40

FIGURE 15. XR16C2852 VOH SOURCE CURRENT CHART ............................................................................................................. 40

AC ELECTRICAL CHARACTERISTICS.............................................................................................................. 41

TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.97V TO 5.5V, 70 PF LOAD WHERE

................................................................................................................................................. 41

FIGURE 16. CLOCK TIMING............................................................................................................................................................. 42

FIGURE 17. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B ................................................................................................. 42

FIGURE 18. DATA BUS READ TIMING.............................................................................................................................................. 43

FIGURE 19. DATA BUS WRITE TIMING ............................................................................................................................................ 43

FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ....................................................... 44

FIGURE 20. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ......................................................... 44

FIGURE 22. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B........................................ 45

FIGURE 23. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B......................................... 45

FIGURE 24. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B ........................... 46

FIGURE 25. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B ............................ 46

PACKAGE DIMENSIONS (44 PIN PLCC) ....................................................................... 47

TABLE OF CONTENTS ............................................................................................................ I

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