REV. 2.3.1 2.97V TO 5.5V UART WITH 128-BYTE FIFO 43 AC ELECTRICAL CHARACTERISTICS TA=0
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參數資料
型號: XR16C850IMTR-F
廠商: Exar Corporation
文件頁數: 38/56頁
文件大?。?/td> 0K
描述: IC UART FIFO 128B 48TQFP
標準包裝: 1,500
特點: *
通道數: 1,UART
FIFO's: 128 字節(jié)
規(guī)程: RS485
電源電壓: 2.97 V ~ 5.5 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調制解調器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應商設備封裝: 48-TQFP(7x7)
包裝: 帶卷 (TR)
xr
XR16C850
REV. 2.3.1
2.97V TO 5.5V UART WITH 128-BYTE FIFO
43
AC ELECTRICAL CHARACTERISTICS
TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.97V TO 5.5V, 70 PF LOAD WHERE
APPLICABLE
SYMBOL
PARAMETER
LIMITS
3.3V
MIN
MAX
LIMITS
5.0V
MIN
MAX
UNIT
CLK
Clock Pulse Duration
45
30
ns
OSC
Crystal Frequency (top mark date code "EC YYWW" and older)
8
24
MHz
OSC
Crystal Frequency (top mark date code "F2 YYWW" and newer)
16
24
MHz
OSC
External Clock Frequency
(top mark date code "EC YYWW" and older)
22
33
MHz
OSC
External Clock Frequency
(top mark date code "F2 YYWW" and newer)
22
36
MHz
TAS
Address Setup Time (AS# tied to GND)
5
0
ns
TAH
Address Hold Time (AS# tied to GND)
(top mark date code of "EC YYWW" and older)
10
5
ns
TAH
Address Hold Time (AS# tied to GND)
(top mark date code of "F2 YYWW" and newer)
0
ns
TCS
Chip Select Width
75
50
ns
TRD
IOR# Strobe Width
75
50
ns
TDY
Read/Write Cycle Delay
75
50
ns
TRDV
Data Access Time
35
25
ns
TDD
Data Disable Time
0
25
0
15
ns
TWR
IOW# Strobe Width
75
50
ns
TDS1
Data Setup Time (AS# tied to GND)
20
15
ns
TDH1
Data Hold Time (AS# tied to GND)
5
ns
TASW
Address Strobe Width
75
50
ns
TAS1
Address Setup Time (AS# used)
5
ns
TAH1
Address Hold Time (AS# used)
10
5
ns
TAS2
Address Setup Time (AS# used)
5
ns
TAH2
Address Hold Time (AS# used)
10
5
ns
TCS1
Delay from Chip Select to AS#
5
ns
TCSH
Delay from AS# to Chip Select
10
5
ns
TCS2
Delay from AS# to Chip Select
5
ns
TRD1
Delay from AS# to Read
10
5
ns
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