參數(shù)資料
型號(hào): XR16C854CJ-F
廠商: Exar Corporation
文件頁數(shù): 45/53頁
文件大小: 0K
描述: IC UART FIFO 128B QUAD 68PLCC
標(biāo)準(zhǔn)包裝: 19
特點(diǎn): *
通道數(shù): 4,QUART
FIFO's: 128 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.97 V ~ 5.5 V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 68-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 68-PLCC
包裝: 管件
其它名稱: 1016-1655
XR16C854CJ-F-ND
XR16C854/854D
5
REV. 3.1.0
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
IOR#
(N.C.)
40
52
66
I
When 16/68# pin is at logic 1, the Intel bus interface is selected
and this input becomes read strobe (active low). The falling edge
instigates an internal read cycle and retrieves the data byte from
an internal register pointed by the address lines [A2:A0], puts the
data byte on the data bus to allow the host processor to read it on
the rising edge.
When 16/68# pin is at logic 0, the Motorola bus interface is
selected and this input is not used.
IOW#
(R/W#)
9
18
15
I
When 16/68# pin is at logic 1, it selects Intel bus interface and this
input becomes write strobe (active low). The falling edge instigates
the internal write cycle and the rising edge transfers the data byte
on the data bus to an internal register pointed by the address lines.
When 16/68# pin is at logic 0, the Motorola bus interface is
selected and this input becomes read (logic 1) and write (logic 0)
signal. Motorola bus interface is not available on the 64 pin pack-
age.
CSA#
(CS#)
7
16
13
I
When 16/68# pin is at logic 1, this input is chip select A (active low)
to enable channel A in the device.
When 16/68# pin is at logic 0, this input becomes the chip select
(active low) for the Motorola bus interface.
Motorola bus interface is not available on the 64 pin package.
CSB#
(A3)
11
20
17
I
When 16/68# pin is at logic 1, this input is chip select B (active low)
to enable channel B in the device.
When 16/68# pin is at logic 0, this input becomes address line A3
which is used for channel selection in the Motorola bus interface.
Motorola bus interface is not available on the 64 pin package.
CSC#
(A4)
38
50
64
I
When 16/68# pin is at logic 1, this input is chip select C (active low)
to enable channel C in the device.
When 16/68# pin is at logic 0, this input becomes address line A4
which is used for channel selection in the Motorola bus interface.
Motorola bus interface is not available on the 64 pin package.
CSD#
(N.C.)
42
54
68
I
When 16/68# pin is at logic 1, this input is chip select D (active low)
to enable channel D in the device.
When 16/68# pin is at logic 0, this input is not used.
Motorola bus interface is not available on the 64 pin package.
INTA
(IRQ#)
6
15
12
O
(OD)
When 16/68# pin is at logic 1 for Intel bus interface, this ouput
becomes channel A interrupt output. The output state is defined by
the user and through the software setting of MCR[3]. INTA is set to
the active mode when MCR[3] is set to a logic 1. INTA is set to the
three state mode when MCR[3] is set to a logic 0 (default). See
MCR[3].
When 16/68# pin is at logic 0 for Motorola bus interface, this output
becomes device interrupt output (active low, open drain). An exter-
nal pull-up resistor is required for proper operation.
Motorola bus interface is not available on the 64 pin package.
Pin Description
NAME
64-LQFP
PIN #
68-PLCC
PIN#
100-QFP
PIN #
TYPE
DESCRIPTION
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