參數(shù)資料
型號: XR16C854CJ-F
廠商: Exar Corporation
文件頁數(shù): 51/53頁
文件大?。?/td> 0K
描述: IC UART FIFO 128B QUAD 68PLCC
標準包裝: 19
特點: *
通道數(shù): 4,QUART
FIFO's: 128 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.97 V ~ 5.5 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調制解調器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 68-LCC(J 形引線)
供應商設備封裝: 68-PLCC
包裝: 管件
其它名稱: 1016-1655
XR16C854CJ-F-ND
XR16C854/854D
7
REV. 3.1.0
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
MODEM OR SERIAL I/O INTERFACE
TXA
TXB
TXC
TXD
8
10
39
41
17
19
51
53
14
16
65
67
O
UART channels A-D Transmit Data and infrared transmit data.
Standard transmit and receive interface is enabled when MCR[6] =
0. In this mode, the TX signal will be a logic 1 during reset, or idle
(no data). Infrared IrDA transmit and receive interface is enabled
when MCR[6] = 1. In the Infrared mode, the inactive state (no
data) for the Infrared encoder/decoder interface is a logic 0.
IRTXA
IRTXB
IRTXC
IRTXD
-
6
24
57
75
O
UART channel A-D Infrared Transmit Data. The inactive state (no
data) for the Infrared encoder/decoder interface is a logic 0.
Regardless of the logic state of MCR bit-6, this pin will be operating
in the Infrared mode.
RXA
RXB
RXC
RXD
62
20
29
51
7
29
41
63
97
34
47
85
I
UART channel A-D Receive Data or infrared receive data. Normal
receive data input must idle at logic 1 condition. The infrared
receiver pulses typically idles at logic 0 but can be inverted by soft-
ware control prior going in to the decoder, see FCTR[2].
RTSA#
RTSB#
RTSC#
RTSD#
5
13
36
44
14
22
48
56
11
19
62
70
O
UART channels A-D Request-to-Send (active low) or general pur-
pose output. This output must be asserted prior to using auto RTS
flow control, see EFR[6], MCR[1], FCTR[1:0], EMSR[5:4] and
IER[6]. Also see
Figure 11. If these outputs are not used, leave
them unconnected.
CTSA#
CTSB#
CTSC#
CTSD#
2
16
33
47
11
25
45
59
8
22
59
73
I
UART channels A-D Clear-to-Send (active low) or general purpose
input. It can be used for auto CTS flow control, see EFR[7], and
IER[7]. Also see
Figure 11. These inputs should be connected
to VCC when not used.
DTRA#
DTRB#
DTRC#
DTRD#
3
15
34
46
12
24
46
58
9
21
60
72
O
UART channels A-D Data-Terminal-Ready (active low) or general
purpose output. If these outputs are not used, leave them uncon-
nected.
DSRA#
DSRB#
DSRC#
DSRD#
1
17
32
48
10
26
44
60
7
23
58
74
I
UART channels A-D Data-Set-Ready (active low) or general pur-
pose input. This input should be connected to VCC when not used.
CDA#
CDB#
CDC#
CDD#
64
18
31
49
9
27
43
61
99
32
49
83
I
UART channels A-D Carrier-Detect (active low) or general purpose
input. This input should be connected to VCC when not used.
RIA#
RIB#
RIC#
RID#
63
19
30
50
8
28
42
62
98
33
48
84
I
UART channels A-D Ring-Indicator (active low) or general purpose
input. This input should be connected to VCC when not used.
ANCILLARY SIGNALS
XTAL1
25
35
40
I
Crystal or external clock input. This input is not 5V tolerant.
Pin Description
NAME
64-LQFP
PIN #
68-PLCC
PIN#
100-QFP
PIN #
TYPE
DESCRIPTION
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