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參數(shù)資料
| 型號(hào)： | XR16C854D |
| 廠商： | Exar Corporation |
| 英文描述： | 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO |
| 中文描述： | 2.97V至5.5V四路UART的128字節(jié)FIFO |
| 文件頁數(shù)： | 6/51頁 |
| 文件大?。?/td> | 476K |
| 代理商： | XR16C854D |
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XR16C854
6
Rev. 1.00P
SYMBOL DESCRIPTION
Symbol
Pin
100
Signal
type
Pin Description
68
64
UARTs (A-D) are enabled when the -CS pin is a logic 0. An
individual UART channel is selected by the data contents of
address bits A3-A4. When the 16 mode is selected (68/100
pin devices), this pin functions as -CSA, see definition under
-CS A-B. This pin is not available on 64 pin packages which
operate in the 16 mode only.
-CS A-B
-CS C-D
16,20
50,54
13,17
64,68
7,11
38,42
I
Chip Select A, B, C, D (active low) - This function is
associated with the 16 mode only, and for individual chan-
nels, A through D. When in 16 Mode, these pins enable
data transfers between the user CPU and the XR16C854 for
the channel(s) addressed. Individual UART sections (A, B,
C, D) are addressed by providing a logic 0 on the respective
-CS A-D pin. When the 68 mode is selected, the functions
of these pins are reassigned. 68 mode functions are de-
scribed under the their respective name/pin headings.
-CSRDY
-
76
-
I
Control Status Ready (active low) - This feature is available
on 100 pin QFP packages only. On 100 pin packages, the
Contents of the FIFORDY Register is read when this pin is
a logic 0. However it should be noted, D0-D3 will contain the
inverted logic states of TXRDY, status bits A-D, and D4-D7
the inverted logic states of RXRDY, status bits D4-D7.
D0-D2
D3-D7
66-68
1-5
88-90
91-95
53-55
56-60
I/O
Data Bus (Bi-directional) - These pins are the eight bit, three
state data bus for transferring information to or from the
controlling CPU. D0 is the least significant bit and the first
data bit in a transmit or receive serial data stream.
GND
GND
6,23
40,57
96,20
46,71
14,28
45,61
Pwr
Signal and power ground.
INT A-B
INT C-D
15,21
49,55
12,18
63,69
6,12
37,43
O
Interrupt A, B, C, D (active high) - This function is associated
with the 16 mode only. These pins provide individual
channel interrupts, INT A-D. INT A-D are enabled when
MCR bit-3 is set to a logic 1, interrupts are enabled in the
interrupt enable register (IER), and when an interrupt con-
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| XR16L2450 | 2.25V TO 5.5V DUART |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16C854DCV | 制造商:Exar Corporation 功能描述: |
| XR16C854DCV-0A-EB | 功能描述:UART 接口集成電路 Supports C854D 64 ld TQFP, ISA Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C854DCV-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C854DCVTR-F | 制造商:Exar Corporation 功能描述:UART 4-CH 128Byte FIFO 3.3V/5V 64-Pin LQFP T/R 制造商:Exar Corporation 功能描述:XR16C854DCVTR-F |
| XR16C854DIV | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO |
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