參數(shù)資料
型號: XR16C854DCV
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: QUAD UART WITH RX/TX FIFO COUNTERS,128-BYTE FIFO
中文描述: 4 CHANNEL(S), 2M bps, SERIAL COMM CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, TQFP-64
文件頁數(shù): 15/51頁
文件大小: 476K
代理商: XR16C854DCV
XR16C854
15
Rev. 1.00P
Table 4, INTERNAL REGISTER DECODE
A2
A1
A0
READ MODE
WRITE MODE
General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR):
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Receive Holding Register
Transmit Holding Register
Interrupt Enable Register
FIFO Control Register
Line Control Register
Modem Control Register
Interrupt Status Register
Line Status Register
Modem Status Register
Scratchpad Register
Scratchpad Register
Baud Rate Register Set (DLL/DLM): Note *2
0
0
0
0
0
1
LSB of Divisor Latch
MSB of Divisor Latch
LSB of Divisor Latch
MSB of Divisor Latch
Enhanced Register Set (EFR, Xon/off 1-2): Note *3
0
0
0
1
1
1
1
0
0
1
0
0
1
1
0
1
0
0
1
0
1
FIFO Trigger Register
FIFO trigger counter
Feature Control Register
Enhanced Feature Register
Xon-1 Word
Xon-2 Word
Xoff-1 Word
Xoff-2 Word
Enhanced Feature Register
Xon-1 Word
Xon-2 Word
Xoff-1 Word
Xoff-2 Word
FIFO Ready Register: Note *4
X
X
X
RXRDY (A-D), TXRDY (A-D)
Note *2: These registers are accessible only when LCR bit-7 is set to a logic 1.
Note *3: Enhanced Feature Register, Xon 1,2 and Xoff 1,2 are accessible only when the LCR is set to
BF(HEX).
Note *4: FIFO Ready Register is available through the CSRDY interface pin only.
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