REV. 1.1.1 2.25V TO 5.5V DUART 7 2.4 Device Identification and Revision The L2450 provides a Device Identification code and a Devi" />
參數(shù)資料
型號(hào)： XR16L2450IM-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 28/30頁(yè)
文件大?。?/td> 0K
描述： IC UART FIFO 1B DUAL 48TQFP
標(biāo)準(zhǔn)包裝： 250
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 1 字節(jié)
規(guī)程： RS232
電源電壓： 2.25 V ~ 5.5 V
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 托盤(pán)
xr
XR16L2450
REV. 1.1.1
2.25V TO 5.5V DUART
7
2.4
Device Identification and Revision
The L2450 provides a Device Identification code and a Device Revision code to distinguish the part from other
devices and revisions. To read the identification code from the part, it is required to set the baud rate generator
registers DLL and DLM both to 0x00. Now reading the content of the DLM will provide 0x02 to indicate L2450
and reading the content of DLL will provide the revision of the part; for example, a reading of 0x01 means
revision A.
2.5
Channel A and B Selection
The UART provides the user with the capability to bi-directionally transfer information between an external
CPU and an external serial communication device. A logic 0 on chip select pins, CSA# or CSB#, allows the
user to select UART channel A or B to configure, send transmit data and/or unload receive data to/from the
UART. Selecting both UARTs can be useful during power up initialization to write to the same internal registers,
but do not attempt to read from both uarts simultaneously. Individual channel select functions are shown in
2.6
Channel A and B Internal Registers
Each UART channel in the L2450 has a standard register set for controlling, monitoring and data loading and
unloading. These registers function as data holding registers (THR/RHR), interrupt status and control registers
(ISR/IER), receive line status and control registers (LSR/LCR), modem status and control registers (MSR/
MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user accessible scratch pad register
(SPR).
2.7
INTA and INTB Outputs
The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup.
Table 2 summarizes the operating behavior for the transmitter and receiver. Also see Figure 12 and Figure 13.
2.8
Crystal Oscillator or External Clock Input
The L2450 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. For programming details, see
“Programmable Baud Rate Generator.”
TABLE 1: CHANNEL A AND B SELECT
CSA#
CSB#
FUNCTION
1
UART de-selected
0
1
Channel A selected
1
0
Channel B selected
0
Channel A and B selected
TABLE 2: INTA AND INTB PINS OPERATION FOR TRANSMITTER
TRANSMITTER
RECEIVER
INTA/B Pin
0 = a byte in THR
1 = THR empty
0 = no data
1 = 1 byte
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