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REV. 1.0.0
XR16L2550
LOW VOLTAGE DUART WITH 16-BYTE FIFO
5
Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain.
1.0
PRODUCT DESCRIPTION
The XR16L2550 (L2550) provides serial asynchronous receive data synchronization, parallel-to-serial and
serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are
RTSB#
15
27
22
O
UART channel B Request-to-Send (active low) or general
purpose output. This output must be asserted prior to
using auto RTS flow control, see EFR[6], MCR[1] and
IER[6]. If it is not used, leave it unconnected.
CTSB#
16
28
23
I
UART channel B Clear-to-Send (active low) or general
purpose input. It can be used for auto CTS flow control,
see EFR[7] and IER[7]. This input should be connected to
VCC when not used.
DTRB#
-
38
35
O
UART channel B Data-Terminal-Ready (active low) or
general purpose output. If it is not used, leave it uncon-
nected.
DSRB#
-
25
20
I
UART channel B Data-Set-Ready (active low) or general
purpose input. This input should be connected to VCC
when not used. This input has no effect on the UART.
CDB#
-
21
16
I
UART channel B Carrier-Detect (active low) or general
purpose input. This input should be connected to VCC
when not used. This input has no effect on the UART.
RIB#
-
26
21
I
UART channel B Ring-Indicator (active low) or general
purpose input. This input should be connected to VCC
when not used. This input has no effect on the UART.
OP2B#
-
15
9
O
Output Port 2 Channel B - The output state is defined by
the user and through the software setting of MCR[3].
INTB is set to the active mode and OP2B# output to a
logic 0 when MCR[3] is set to a logic 1. INTB is set to the
three state mode and OP2B# to a logic 1 when MCR[3] is
set to a logic 0. This output should not be used as a gen-
eral output else it will disturb the INTB output functionality.
If it is not used, leave it unconnected.
ANCILLARY SIGNALS
XTAL1
10
18
13
I
Crystal or external clock input.
XTAL2
11
19
14
O
Crystal or buffered clock output.
RESET
24
39
36
I
Reset (active high) - A longer than 40 ns logic 1 pulse on
this pin will reset the internal registers and all outputs.
The UART transmitter output will be held at logic 1, the
receiver input will be ignored and outputs are reset during
reset period.
VCC
26
44
42
Pwr
2.25V to 5.5V power supply. All inputs are 5V tolerant.
GND
13
22
17
Pwr
Power supply common, ground.
N.C.
9, 17
-
12, 24, 25,
37
No Connection. These pins are open, but typically, should
be connected to GND for good design practice.
Pin Description
N
AME
32-QFN
P
IN
#
44-PLCC
P
IN
#
48-TQFP
P
IN
#
T
YPE
D
ESCRIPTION