參數(shù)資料
型號(hào)： XR16L2550IL
廠商： EXAR CORP
元件分類： 微控制器/微處理器
英文描述： LOW VOLTAGE DUART WITH 16-BYTE FIFO
中文描述： 2 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, QCC32
封裝： 5 X 5 MM, 0.90 MM HEIGHT, QFN-32
文件頁數(shù)： 3/45頁
文件大?。?/td> 278K
代理商： XR16L2550IL
á
REV. 1.0.0
XR16L2550
LOW VOLTAGE DUART WITH 16-BYTE FIFO
3
PIN DESCRIPTIONS
Pin Description
N
AME
32-QFN
P
IN
#
44-PLCC
P
IN
#
48-TQFP
P
IN
#
T
YPE
D
ESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
18
19
20
29
30
31
26
27
28
I
Address data lines [2:0]. These 3 address lines select
one of the internal registers in UART channel A/B during
a data bus transaction.
D7
D6
D5
D4
D3
D2
D1
D0
2
1
32
31
30
29
28
27
9
8
7
6
5
4
3
2
3
2
1
48
47
46
45
44
IO
Data bus lines [7:0] (bidirectional).
IOR#
14
24
19
I
Input/Output Read Strobe (active low). The falling edge
instigates an internal read cycle and retrieves the data
byte from an internal register pointed to by the address
lines [A2:A0]. The data byte is placed on the data bus to
allow the host processor to read it on the rising edge.
IOW#
12
20
15
I
Input/Output Write Strobe (active low). The falling edge
instigates an internal write cycle and the rising edge
transfers the data byte on the data bus to an internal reg-
ister pointed by the address lines.
CSA#
7
16
10
I
UART channel A select (active low) to enable UART chan-
nel A in the device for data bus operation.
CSB#
8
17
11
I
UART channel B select (active low) to enable UART chan-
nel B in the device for data bus operation.
INTA
22
33
30
O
UART channel A Interrupt output. The output state is
defined by the user and through the software setting of
MCR[3]. INTA is set to the active mode (active high) and
OP2A# output to a logic 0 when MCR[3] is set to a logic
1. INTA is set to the three state mode and OP2A# to a
logic 1 when MCR[3] is set to a logic 0 (Default).
INTB
21
32
29
O
UART channel B Interrupt output. The output state is
defined by the user and through the software setting of
MCR[3]. INTB is set to the active mode and OP2B# out-
put to a logic 0 when MCR[3] is set to a logic 1. INTB is
set to the three state mode and OP2B# to a logic 1 when
MCR[3] is set to a logic 0 (Default).
TXRDYA#
-
1
43
O
UART channel A Transmitter Ready (active low). The
output provides the TX FIFO/THR status for transmit
channel A. If it is not used, leave it unconnected.
RXRDYA#
-
34
31
O
UART channel A Receiver Ready (active low). This output
provides the RX FIFO/RHR status for receive channel A.
If it is not used, leave it unconnected.
相關(guān)PDF資料
PDF描述
XR16L2550IM LOW VOLTAGE DUART WITH 16-BYTE FIFO
XR16L2550 LOW VOLTAGE DUART WITH 16-BYTE FIFO
XR16L2551 LOW VOLTAGE DUART WITH POWERSAVE
XR16L2551IL LOW VOLTAGE DUART WITH POWERSAVE
XR16L2551IM LOW VOLTAGE DUART WITH POWERSAVE
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XR16L2550IL-F 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR16L2550ILTR-F 制造商:Exar Corporation 功能描述:UART 2-CH 16Byte FIFO 2.5V/3.3V/5V 32-Pin QFN EP T/R 制造商:Exar Corporation 功能描述:XR16L2550ILTR-F
XR16L2550IM 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述:
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